+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2010 by Drasko DRASKOVIC *
* drasko.draskovic@gmail.com *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#define NB_CACHE_WAYS 4
-static uint32_t dc;
-static uint32_t ic;
+#define CP15_CTL 0x02
+#define CP15_CTL_DCACHE (1<<2)
+#define CP15_CTL_ICACHE (1<<12)
/**
* flag to give info about cache manipulation during debug :
* "0" - cache lines are invalidated "on the fly", for affected addresses.
- * This is prefered from performance point of view.
+ * This is preferred from performance point of view.
* "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
* It is kept off during debugging.
*/
static uint8_t arm946e_preserve_cache;
-int arm946e_post_debug_entry(struct target *target);
-void arm946e_pre_restore_context(struct target *target);
+static int arm946e_post_debug_entry(struct target *target);
+static void arm946e_pre_restore_context(struct target *target);
static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value);
-int arm946e_init_arch_info(struct target *target,
+static int arm946e_init_arch_info(struct target *target,
struct arm946e_common *arm946e,
struct jtag_tap *tap)
{
return ERROR_OK;
}
-static int arm946e_verify_pointer(struct command_context *cmd_ctx,
+static void arm946e_deinit_target(struct target *target)
+{
+ struct arm *arm = target_to_arm(target);
+ struct arm946e_common *arm946e = target_to_arm946(target);
+
+ arm7_9_deinit(target);
+ arm_free_reg_cache(arm);
+ free(arm946e);
+}
+
+static int arm946e_verify_pointer(struct command_invocation *cmd,
struct arm946e_common *arm946e)
{
if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
- command_print(cmd_ctx, "target is not an ARM946");
+ command_print(cmd, "target is not an ARM946");
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
}
+/*
+ * Update cp15_control_reg, saved on debug_entry.
+ */
+static void arm946e_update_cp15_caches(struct target *target, uint32_t value)
+{
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ arm946e->cp15_control_reg = (arm946e->cp15_control_reg & ~(CP15_CTL_DCACHE|CP15_CTL_ICACHE))
+ | (value & (CP15_CTL_DCACHE|CP15_CTL_ICACHE));
+}
+
/*
* REVISIT: The "read_cp15" and "write_cp15" commands could hook up
* to eventual mrc() and mcr() routines ... the reg_addr values being
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
+static int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-uint32_t arm946e_invalidate_whole_dcache(struct target *target)
-{
-
- uint32_t csize = 0;
- uint32_t shift = 0;
- uint32_t cp15_idx, seg, dtag;
- int nb_idx, idx = 0;
- int retval;
+#define GET_ICACHE_SIZE 6
+#define GET_DCACHE_SIZE 18
- /* Get cache type */
- arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);
-
- csize = (csize >> 18) & 0x0F;
+/*
+ * \param target struct target pointer
+ * \param idsel select GET_ICACHE_SIZE or GET_DCACHE_SIZE
+ * \returns cache size, given in bytes
+ */
+static uint32_t arm946e_cp15_get_csize(struct target *target, int idsel)
+{
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ uint32_t csize = arm946e->cp15_cache_info;
+ if (csize == 0) {
+ if (arm946e_read_cp15(target, 0x01, &csize) == ERROR_OK)
+ arm946e->cp15_cache_info = csize;
+ }
+ if (csize & (1<<(idsel-4))) /* cache absent */
+ return 0;
+ csize = (csize >> idsel) & 0x0F;
+ return csize ? 1 << (12 + (csize-3)) : 0;
+}
+static uint32_t arm946e_invalidate_whole_dcache(struct target *target)
+{
+ uint32_t csize = arm946e_cp15_get_csize(target, GET_DCACHE_SIZE);
if (csize == 0)
- shift = 0;
- else
- shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- /* Cache size, given in bytes */
- csize = 1 << (12 + shift);
- /* One line (index) is 32 bytes (8 words) long */
- nb_idx = (csize / 32); /* gives nb of lines (indexes) in the cache */
+ /* One line (index) is 32 bytes (8 words) long, 4-way assoc
+ * ARM DDI 0201D, Section 3.3.5
+ */
+ int nb_idx = (csize / (4*8*NB_CACHE_WAYS)); /* gives nb of lines (indexes) in the cache */
- /* Loop for all segmentde (i.e. ways) */
+ /* Loop for all segments (i.e. ways) */
+ uint32_t seg;
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
/* Loop for all indexes */
+ int idx;
for (idx = 0; idx < nb_idx; idx++) {
/* Form and write cp15 index (segment + line idx) */
- cp15_idx = seg << 30 | idx << 5;
- retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
+ uint32_t cp15_idx = seg << 30 | idx << 5;
+ int retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
/* Read dtag */
- arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
+ uint32_t dtag;
+ retval = arm946e_read_cp15(target, 0x16, &dtag);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("ERROR reading dtag");
+ return retval;
+ }
/* Check cache line VALID bit */
if (!(dtag >> 4 & 0x1))
return ERROR_OK;
}
-uint32_t arm946e_invalidate_whole_icache(struct target *target)
+static uint32_t arm946e_invalidate_whole_icache(struct target *target)
{
- int retval;
+ /* Check cache presence before flushing - avoid undefined behavior */
+ uint32_t csize = arm946e_cp15_get_csize(target, GET_ICACHE_SIZE);
+ if (csize == 0)
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
LOG_DEBUG("FLUSHING I$");
-
/**
* Invalidate (flush) I$
* mcr 15, 0, r0, cr7, cr5, {0}
*/
- retval = arm946e_write_cp15(target, 0x0f, 0x1);
+ int retval = arm946e_write_cp15(target, 0x0f, 0x1);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing I$");
return retval;
return ERROR_OK;
}
-int arm946e_post_debug_entry(struct target *target)
+static int arm946e_post_debug_entry(struct target *target)
{
uint32_t ctr_reg = 0x0;
uint32_t retval = ERROR_OK;
+ struct arm946e_common *arm946e = target_to_arm946(target);
/* See if CACHES are enabled, and save that info
- * in the global vars, so that arm946e_pre_restore_context() can use them */
- arm946e_read_cp15(target, 0x02, (uint32_t *) &ctr_reg);
- dc = (ctr_reg >> 2) & 0x01;
- ic = (ctr_reg >> 12) & 0x01;
+ * in the context bits, so that arm946e_pre_restore_context() can use them */
+ arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
+
+ /* Save control reg in the context */
+ arm946e->cp15_control_reg = ctr_reg;
if (arm946e_preserve_cache) {
- if (dc == 1) {
+ if (ctr_reg & CP15_CTL_DCACHE) {
/* Clean and flush D$ */
arm946e_invalidate_whole_dcache(target);
/* Disable D$ */
- ctr_reg &= ~(1 << 2);
+ ctr_reg &= ~CP15_CTL_DCACHE;
}
- if (ic == 1) {
+ if (ctr_reg & CP15_CTL_ICACHE) {
/* Flush I$ */
arm946e_invalidate_whole_icache(target);
/* Disable I$ */
- ctr_reg &= ~(1 << 12);
+ ctr_reg &= ~CP15_CTL_ICACHE;
}
/* Write the new configuration */
- retval = arm946e_write_cp15(target, 0x02, ctr_reg);
+ retval = arm946e_write_cp15(target, CP15_CTL, ctr_reg);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR disabling cache");
return retval;
return ERROR_OK;
}
-void arm946e_pre_restore_context(struct target *target)
+static void arm946e_pre_restore_context(struct target *target)
{
uint32_t ctr_reg = 0x0;
uint32_t retval;
if (arm946e_preserve_cache) {
+ struct arm946e_common *arm946e = target_to_arm946(target);
/* Get the contents of the CTR reg */
- arm946e_read_cp15(target, 0x02, (uint32_t *) &ctr_reg);
+ arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
/**
- * Read-modify-write CP15 test state register
- * to reenable I/D-cache linefills
+ * Read-modify-write CP15 control
+ * to reenable I/D-cache operation
+ * NOTE: It is not possible to disable cache by CP15.
+ * if arm946e_preserve_cache debugging flag enabled.
*/
- if (dc == 1) {
- /* Enable D$ */
- ctr_reg |= 1 << 2;
- }
-
- if (ic == 1) {
- /* Enable I$ */
- ctr_reg |= 1 << 12;
- }
+ ctr_reg |= arm946e->cp15_control_reg & (CP15_CTL_DCACHE|CP15_CTL_ICACHE);
/* Write the new configuration */
- retval = arm946e_write_cp15(target, 0x02, ctr_reg);
+ retval = arm946e_write_cp15(target, CP15_CTL, ctr_reg);
if (retval != ERROR_OK)
LOG_DEBUG("ERROR enabling cache");
} /* if preserve_cache */
}
-uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
+static uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
{
- uint32_t csize = 0x0;
- uint32_t shift = 0;
uint32_t cur_addr = 0x0;
uint32_t cp15_idx, set, way, dtag;
uint32_t i = 0;
for (i = 0; i < count*size; i++) {
cur_addr = address + i;
- /* Get cache type */
- arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);
-
- /* Conclude cache size to find number of lines */
- csize = (csize >> 18) & 0x0F;
-
- if (csize == 0)
- shift = 0;
- else
- shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
-
- csize = 1 << (12 + shift);
set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
}
/* Read dtag */
- arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
+ retval = arm946e_read_cp15(target, 0x16, &dtag);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("ERROR reading dtag");
+ return retval;
+ }
/* Check cache line VALID bit */
if (!(dtag >> 4 & 0x1))
return ERROR_OK;
}
-uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
+static uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
{
uint32_t cur_addr = 0x0;
}
/* Read itag */
- arm946e_read_cp15(target, 0x17, (uint32_t *) &itag);
+ retval = arm946e_read_cp15(target, 0x17, &itag);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("ERROR reading itag");
+ return retval;
+ }
/* Check cache line VALID bit */
if (!(itag >> 4 & 0x1))
}
/** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm946e_write_memory(struct target *target, uint32_t address,
+static int arm946e_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
LOG_DEBUG("-");
+ struct arm946e_common *arm946e = target_to_arm946(target);
/* Invalidate D$ if it is ON */
- if (!arm946e_preserve_cache && dc == 1)
+ if (!arm946e_preserve_cache && (arm946e->cp15_control_reg & CP15_CTL_DCACHE))
arm946e_invalidate_dcache(target, address, size, count);
/**
* Write memory
*/
- retval = arm7_9_write_memory(target, address, size, count, buffer);
+ retval = arm7_9_write_memory_opt(target, address, size, count, buffer);
if (retval != ERROR_OK)
return retval;
* the cache write policy is write-through.
* If the data is not in the cache, the controller writes to main memory only.
*/
- if (!arm946e_preserve_cache && ic == 1)
+ if (!arm946e_preserve_cache && (arm946e->cp15_control_reg & CP15_CTL_ICACHE))
arm946e_invalidate_icache(target, address, size, count);
return ERROR_OK;
}
-int arm946e_read_memory(struct target *target, uint32_t address,
+static int arm946e_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
return ERROR_OK;
}
+COMMAND_HANDLER(arm946e_handle_cp15)
+{
+ /* one or two arguments, access a single register (write if second argument is given) */
+ if (CMD_ARGC < 1 || CMD_ARGC > 2)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct target *target = get_current_target(CMD_CTX);
-COMMAND_HANDLER(arm946e_handle_cp15_command)
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ int retval = arm946e_verify_pointer(CMD, arm946e);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->state != TARGET_HALTED) {
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ uint32_t address;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+
+ if (CMD_ARGC == 1) {
+ uint32_t value;
+ retval = arm946e_read_cp15(target, address, &value);
+ if (retval != ERROR_OK) {
+ command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
+ return retval;
+ }
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Return value in hex format */
+ command_print(CMD, "0x%08" PRIx32, value);
+ } else if (CMD_ARGC == 2) {
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+
+ retval = arm946e_write_cp15(target, address, value);
+ if (retval != ERROR_OK) {
+ command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
+ return retval;
+ }
+ if (address == CP15_CTL)
+ arm946e_update_cp15_caches(target, value);
+ }
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(arm946e_handle_idcache)
{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm946e_common *arm946e = target_to_arm946(target);
- retval = arm946e_verify_pointer(CMD_CTX, arm946e);
+ retval = arm946e_verify_pointer(CMD, arm946e);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ bool icache = (strcmp(CMD_NAME, "icache") == 0);
+ uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024;
+ if (CMD_ARGC == 0) {
+ bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
+ && (arm946e->cp15_control_reg & 0x1);
+ if (csize == 0)
+ command_print(CMD, "%s-cache absent", icache ? "I" : "D");
+ else
+ command_print(CMD, "%s-cache size: %" PRIu32 "K, %s",
+ icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
return ERROR_OK;
}
- /* one or more argument, access a single register (write if second argument is given */
- if (CMD_ARGC >= 1) {
- uint32_t address;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ bool flush = false;
+ bool enable = false;
+ retval = command_parse_bool_arg(CMD_ARGV[0], &enable);
+ if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
+ if (strcmp(CMD_ARGV[0], "flush") == 0) {
+ flush = true;
+ retval = ERROR_OK;
+ } else
+ return retval;
+ }
- if (CMD_ARGC == 1) {
- uint32_t value;
- retval = arm946e_read_cp15(target, address, &value);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
- return ERROR_OK;
- }
- retval = jtag_execute_queue();
- if (retval != ERROR_OK)
- return retval;
+ /* Do not invalidate or change state, if cache is absent */
+ if (csize == 0) {
+ command_print(CMD, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
- } else if (CMD_ARGC == 2) {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
- retval = arm946e_write_cp15(target, address, value);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
- return ERROR_OK;
- }
- command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
- }
+ /* NOTE: flushing entire cache will not preserve lock-down cache regions */
+ if (icache) {
+ if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable)
+ retval = arm946e_invalidate_whole_icache(target);
+ } else {
+ if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable)
+ retval = arm946e_invalidate_whole_dcache(target);
}
+ if (retval != ERROR_OK || flush)
+ return retval;
+
+ uint32_t value;
+ retval = arm946e_read_cp15(target, CP15_CTL, &value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ uint32_t vnew = value;
+ uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE;
+ if (enable) {
+ if ((value & 0x1) == 0)
+ LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
+ vnew |= cmask;
+ } else
+ vnew &= ~cmask;
+
+ if (vnew == value)
+ return ERROR_OK;
+
+ retval = arm946e_write_cp15(target, CP15_CTL, vnew);
+ if (retval != ERROR_OK)
+ return retval;
+
+ arm946e_update_cp15_caches(target, vnew);
return ERROR_OK;
}
static const struct command_registration arm946e_exec_command_handlers[] = {
{
.name = "cp15",
- .handler = arm946e_handle_cp15_command,
+ .handler = arm946e_handle_cp15,
.mode = COMMAND_EXEC,
.usage = "regnum [value]",
- .help = "display/modify cp15 register",
+ .help = "read/modify cp15 register",
+ },
+ {
+ .name = "icache",
+ .handler = arm946e_handle_idcache,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable'|'flush']",
+ .help = "I-cache info and operations",
+ },
+ {
+ .name = "dcache",
+ .handler = arm946e_handle_idcache,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable'|'flush']",
+ .help = "D-cache info and operations",
},
COMMAND_REGISTRATION_DONE
};
-const struct command_registration arm946e_command_handlers[] = {
+static const struct command_registration arm946e_command_handlers[] = {
{
.chain = arm9tdmi_command_handlers,
},
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
+ .get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = arm_get_gdb_reg_list,
/* .read_memory = arm7_9_read_memory, */
.read_memory = arm946e_read_memory,
.write_memory = arm946e_write_memory,
- .bulk_write_memory = arm7_9_bulk_write_memory,
-
.checksum_memory = arm_checksum_memory,
.blank_check_memory = arm_blank_check_memory,
.commands = arm946e_command_handlers,
.target_create = arm946e_target_create,
.init_target = arm9tdmi_init_target,
+ .deinit_target = arm946e_deinit_target,
.examine = arm7_9_examine,
.check_reset = arm7_9_check_reset,
};
projects / fw / openocd / blobdiff