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cleanup: rename armv4_5 to arm for readability
[fw/openocd] / src / target / arm926ejs.c
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 0cf7173564b6bf6203cb8877a94af7b0e573963e..aaf4021afc675727e2983bd00840e426fc63ad1b 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -67,7 +67,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
@@ -120,7 +122,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -155,7 +159,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = value_buf;
@@ -205,7 +211,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -337,20 +345,27 @@ static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
        return ERROR_OK;
 }
 
-static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
        {
                /* invalidate TLB */
-               arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x1U;
        }
@@ -360,17 +375,25 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
                uint32_t debug_override;
                /* read-modify-write CP15 debug override register
                 * to enable "test and clean all" */
-               arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+               retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
                debug_override |= 0x80000;
-               arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* clean and invalidate DCache */
-               arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* write CP15 debug override register
                 * to disable "test and clean all" */
                debug_override &= ~0x80000;
-               arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x4U;
        }
@@ -378,23 +401,31 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
        {
                /* invalidate ICache */
-               arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x1000U;
        }
 
-       arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       return retval;
 }
 
-static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -405,24 +436,34 @@ static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control |= 0x1000U;
 
-       arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       return retval;
 }
 
-static void arm926ejs_post_debug_entry(struct target *target)
+static int arm926ejs_post_debug_entry(struct target *target)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
        if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
                uint32_t cache_type_reg;
                /* identify caches */
-               arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
-               jtag_execute_queue();
+               retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
        }
 
@@ -431,9 +472,15 @@ static void arm926ejs_post_debug_entry(struct target *target)
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
        /* save i/d fault status and address register */
-       arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
-       arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
-       arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       if (retval != ERROR_OK)
+               return retval;
 
        LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
                arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
@@ -442,9 +489,12 @@ static void arm926ejs_post_debug_entry(struct target *target)
 
        /* read-modify-write CP15 cache debug control register
         * to disable I/D-cache linefills and force WT */
-       arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       if (retval != ERROR_OK)
+               return retval;
        cache_dbg_ctrl |= 0x7;
-       arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       return retval;
 }
 
 static void arm926ejs_pre_restore_context(struct target *target)
@@ -486,7 +536,6 @@ int arm926ejs_arch_state(struct target *target)
        };
 
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
-       struct arm *armv4_5;
 
        if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
        {
@@ -494,8 +543,6 @@ int arm926ejs_arch_state(struct target *target)
                return ERROR_TARGET_INVALID;
        }
 
-       armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                         state[arm926ejs->armv4_5_mmu.mmu_enabled],
@@ -510,7 +557,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
        int retval = ERROR_OK;
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       struct arm *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *arm = &arm7_9->arm;
        struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        if ((retval = target_halt(target)) != ERROR_OK)
@@ -553,18 +600,20 @@ int arm926ejs_soft_reset_halt(struct target *target)
        /* SVC, ARM state, IRQ and FIQ disabled */
        uint32_t cpsr;
 
-       cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+       cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
        cpsr &= ~0xff;
        cpsr |= 0xd3;
-       arm_set_cpsr(armv4_5, cpsr);
-       armv4_5->cpsr->dirty = 1;
+       arm_set_cpsr(arm, cpsr);
+       arm->cpsr->dirty = 1;
 
        /* start fetching from 0x0 */
-       buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
-       armv4_5->pc->dirty = 1;
-       armv4_5->pc->valid = 1;
+       buf_set_u32(arm->pc->value, 0, 32, 0x0);
+       arm->pc->dirty = 1;
+       arm->pc->valid = 1;
 
-       arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+       retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+       if (retval != ERROR_OK)
+               return retval;
        arm926ejs->armv4_5_mmu.mmu_enabled = 0;
        arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
@@ -574,7 +623,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
 int arm926ejs_write_memory(struct target *target, uint32_t address,
-               uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
@@ -641,7 +690,7 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
 
 static int arm926ejs_write_phys_memory(struct target *target,
                uint32_t address, uint32_t size,
-               uint32_t count, uint8_t *buffer)
+               uint32_t count, const uint8_t *buffer)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
@@ -664,8 +713,8 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
 {
        struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
 
-       arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
-       arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
+       arm7_9->arm.mrc = arm926ejs_mrc;
+       arm7_9->arm.mcr = arm926ejs_mcr;
 
        /* initialize arm7/arm9 specific info (including armv4_5) */
        arm9tdmi_init_arch_info(target, arm7_9, tap);
@@ -752,6 +801,7 @@ static const struct command_registration arm926ejs_exec_command_handlers[] = {
                .name = "cache_info",
                .handler = arm926ejs_handle_cache_info_command,
                .mode = COMMAND_EXEC,
+               .usage = "",
                .help = "display information about target caches",
 
        },
@@ -765,6 +815,7 @@ const struct command_registration arm926ejs_command_handlers[] = {
                .name = "arm926ejs",
                .mode = COMMAND_ANY,
                .help = "arm926ejs command group",
+               .usage = "",
                .chain = arm926ejs_exec_command_handlers,
        },
        COMMAND_REGISTRATION_DONE
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