projects / fw / openocd / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
jim tests: use installed
[fw/openocd] / src / target / arm926ejs.c
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d68e5ca342a2d27fb434348520428adde67d4446..3765f23135cc2293463730863f0705a66882c00f 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -67,7 +67,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
@@ -120,7 +122,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -155,7 +159,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = value_buf;
@@ -205,7 +211,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -323,7 +331,7 @@ static int arm926ejs_examine_debug_reason(struct target *target)
        return ERROR_OK;
 }
 
-static uint32_t arm926ejs_get_ttb(struct target *target)
+static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        int retval;
@@ -332,23 +340,32 @@ static uint32_t arm926ejs_get_ttb(struct target *target)
        if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
                return retval;
 
-       return ttb;
+       *result = ttb;
+
+       return ERROR_OK;
 }
 
-static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
        {
                /* invalidate TLB */
-               arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x1U;
        }
@@ -358,17 +375,25 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
                uint32_t debug_override;
                /* read-modify-write CP15 debug override register
                 * to enable "test and clean all" */
-               arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+               retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
                debug_override |= 0x80000;
-               arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* clean and invalidate DCache */
-               arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* write CP15 debug override register
                 * to disable "test and clean all" */
                debug_override &= ~0x80000;
-               arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x4U;
        }
@@ -376,23 +401,31 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
        {
                /* invalidate ICache */
-               arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x1000U;
        }
 
-       arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       return retval;
 }
 
-static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -403,24 +436,34 @@ static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control |= 0x1000U;
 
-       arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       return retval;
 }
 
-static void arm926ejs_post_debug_entry(struct target *target)
+static int arm926ejs_post_debug_entry(struct target *target)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
        if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
                uint32_t cache_type_reg;
                /* identify caches */
-               arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
-               jtag_execute_queue();
+               retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
        }
 
@@ -429,9 +472,15 @@ static void arm926ejs_post_debug_entry(struct target *target)
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
        /* save i/d fault status and address register */
-       arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
-       arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
-       arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       if (retval != ERROR_OK)
+               return retval;
 
        LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
                arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
@@ -440,9 +489,12 @@ static void arm926ejs_post_debug_entry(struct target *target)
 
        /* read-modify-write CP15 cache debug control register
         * to disable I/D-cache linefills and force WT */
-       arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       if (retval != ERROR_OK)
+               return retval;
        cache_dbg_ctrl |= 0x7;
-       arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       return retval;
 }
 
 static void arm926ejs_pre_restore_context(struct target *target)
@@ -562,7 +614,9 @@ int arm926ejs_soft_reset_halt(struct target *target)
        armv4_5->pc->dirty = 1;
        armv4_5->pc->valid = 1;
 
-       arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+       retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+       if (retval != ERROR_OK)
+               return retval;
        arm926ejs->armv4_5_mmu.mmu_enabled = 0;
        arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
openocd with support for Altus Metrum targets