int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm926ejs_quit();
-int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size);
+int arm926ejs_arch_state(struct target_s *target);
int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm926ejs_soft_reset_halt(struct target_s *target);
+static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
+static int arm926ejs_mmu(struct target_s *target, int *enabled);
target_type_t arm926ejs_target =
{
.register_commands = arm926ejs_register_commands,
.target_command = arm926ejs_target_command,
.init_target = arm926ejs_init_target,
- .quit = arm926ejs_quit
+ .quit = arm926ejs_quit,
+ .virt2phys = arm926ejs_virt2phys,
+ .mmu = arm926ejs_mmu
};
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
- jtag_add_dr_scan(4, fields, -1, NULL);
+ jtag_add_dr_scan(4, fields, -1);
fields[0].in_handler_priv = value;
fields[0].in_handler = arm_jtag_buf_to_u32;
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
- jtag_add_dr_scan(4, fields, -1, NULL);
+ jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
} while (buf_get_u32(&access, 0, 1) != 1);
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
- jtag_add_dr_scan(4, fields, -1, NULL);
+ jtag_add_dr_scan(4, fields, -1);
do
{
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
- jtag_add_dr_scan(4, fields, -1, NULL);
+ jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
} while (buf_get_u32(&access, 0, 1) != 1);
default:
ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
target->debug_reason = DBG_REASON_DBGRQ;
+ retval = ERROR_TARGET_FAILURE;
+ break;
}
- return ERROR_OK;
+ return retval;
}
u32 arm926ejs_get_ttb(target_t *target)
return ERROR_OK;
}
-int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size)
+int arm926ejs_arch_state(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
exit(-1);
}
- snprintf(buf, buf_size,
+ USER(
"target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- if (target->state == TARGET_RUNNING)
- {
- target->type->halt(target);
- }
+ target->type->halt(target);
while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
int chain_pos;
char *variant = NULL;
arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
+ memset(arm926ejs, 0, sizeof(*arm926ejs));
if (argc < 4)
{
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
}
+static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
+{
+ int retval;
+ int type;
+ u32 cb;
+ int domain;
+ u32 ap;
+
+ armv4_5_common_t *armv4_5;
+ arm7_9_common_t *arm7_9;
+ arm9tdmi_common_t *arm9tdmi;
+ arm926ejs_common_t *arm926ejs;
+ retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
+ u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
+ if (type == -1)
+ {
+ return ret;
+ }
+ *physical = ret;
+ return ERROR_OK;
+}
+
+static int arm926ejs_mmu(struct target_s *target, int *enabled)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
+
+ if (target->state != TARGET_HALTED)
+ {
+ ERROR("Target not halted");
+ return ERROR_TARGET_INVALID;
+ }
+ *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
+ return ERROR_OK;
+}