#ifndef ARM920T_H
#define ARM920T_H
-#include "target.h"
-#include "register.h"
-#include "embeddedice.h"
-#include "arm_jtag.h"
#include "arm9tdmi.h"
#include "armv4_5_mmu.h"
-#include "armv4_5_cache.h"
#define ARM920T_COMMON_MAGIC 0xa920a920
-typedef struct arm920t_common_s
+struct arm920t_common
{
- u32 common_magic;
- armv4_5_mmu_common_t armv4_5_mmu;
- arm9tdmi_common_t arm9tdmi_common;
- u32 cp15_control_reg;
- u32 d_fsr;
- u32 i_fsr;
- u32 d_far;
- u32 i_far;
+ struct arm9tdmi_common arm9tdmi_common;
+ uint32_t common_magic;
+ struct armv4_5_mmu_common armv4_5_mmu;
+ uint32_t cp15_control_reg;
+ uint32_t d_fsr;
+ uint32_t i_fsr;
+ uint32_t d_far;
+ uint32_t i_far;
int preserve_cache;
-} arm920t_common_t;
+};
-typedef struct arm920t_cache_line_s
+static inline struct arm920t_common *
+target_to_arm920(struct target *target)
{
- u32 cam;
- u32 data[8];
-} arm920t_cache_line_t;
+ return container_of(target->arch_info, struct arm920t_common,
+ arm9tdmi_common.arm7_9_common.armv4_5_common);
+}
-typedef struct arm920t_tlb_entry_s
+struct arm920t_cache_line
{
- u32 cam;
- u32 ram1;
- u32 ram2;
-} arm920t_tlb_entry_t;
+ uint32_t cam;
+ uint32_t data[8];
+};
+
+struct arm920t_tlb_entry
+{
+ uint32_t cam;
+ uint32_t ram1;
+ uint32_t ram2;
+};
+
+int arm920t_arch_state(struct target *target);
+int arm920t_soft_reset_halt(struct target *target);
+int arm920t_read_memory(struct target *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm920t_write_memory(struct target *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+void arm920t_post_debug_entry(struct target *target);
+void arm920t_pre_restore_context(struct target *target);
+ uint32_t arm920t_get_ttb(struct target *target);
+void arm920t_disable_mmu_caches(struct target *target,
+ int mmu, int d_u_cache, int i_cache);
+void arm920t_enable_mmu_caches(struct target *target,
+ int mmu, int d_u_cache, int i_cache);
+int arm920t_register_commands(struct command_context_s *cmd_ctx);
#endif /* ARM920T_H */