dsp5680xx - mark erase after unlocking flash

[fw/openocd] / src / target / arm920t.c

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index c5064c1126d4058540c0259818fdd71d85e81936..f057d7b9b485eb3e101cfb221a354127955d47ab 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -93,7 +93,9 @@ static int arm920t_read_cp15_physical(struct target *target,
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
        retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
        if (retval != ERROR_OK)
                return retval;
@@ -146,7 +148,9 @@ static int arm920t_write_cp15_physical(struct target *target,
 
        buf_set_u32(value_buf, 0, 32, value);
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
        retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
        if (retval != ERROR_OK)
                return retval;
@@ -197,7 +201,9 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
        retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
        if (retval != ERROR_OK)
                return retval;
@@ -275,7 +281,10 @@ static int arm920t_read_cp15_interpreted(struct target *target,
 #endif
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -317,7 +326,10 @@ int arm920t_write_cp15_interpreted(struct target *target,
 #endif
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -521,7 +533,6 @@ int arm920t_arch_state(struct target *target)
        };
 
        struct arm920t_common *arm920t = target_to_arm920(target);
-       struct arm *armv4_5;
 
        if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
        {
@@ -529,8 +540,6 @@ int arm920t_arch_state(struct target *target)
                return ERROR_TARGET_INVALID;
        }
 
-       armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                 state[arm920t->armv4_5_mmu.mmu_enabled],
@@ -590,7 +599,7 @@ static int arm920t_read_phys_memory(struct target *target,
 
 static int arm920t_write_phys_memory(struct target *target,
                uint32_t address, uint32_t size,
-               uint32_t count, uint8_t *buffer)
+               uint32_t count, const uint8_t *buffer)
 {
        struct arm920t_common *arm920t = target_to_arm920(target);
 
@@ -601,7 +610,7 @@ static int arm920t_write_phys_memory(struct target *target,
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
 int arm920t_write_memory(struct target *target, uint32_t address,
-               uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */
@@ -886,7 +895,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        uint32_t C15_C_D_Ind, C15_C_I_Ind;
        int i;
        FILE *output;
-       struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
        int segment, index_t;
        struct reg *r;
 
@@ -995,8 +1003,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       d_cache[segment][index_t].cam = regs[9];
-
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
@@ -1006,7 +1012,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
                        for (i = 1; i < 9; i++)
                        {
-                                d_cache[segment][index_t].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }
@@ -1103,8 +1108,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       i_cache[segment][index_t].cam = regs[9];
-
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, "
@@ -1114,7 +1117,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
                        for (i = 1; i < 9; i++)
                        {
-                                i_cache[segment][index_t].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }
@@ -1148,7 +1150,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        fclose(output);
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
        r = armv4_5->core_cache->reg_list;
@@ -1475,7 +1480,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        fclose(output);
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
        r = armv4_5->core_cache->reg_list;