jtag_info = &arm920t->arm7_9_common.jtag_info;
- arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+ retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
buf_set_u32(value_buf, 0, 32, value);
- arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+ retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
jtag_info = &arm920t->arm7_9_common.jtag_info;
- arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+ retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
#endif
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
r[0].dirty = 1;
r[1].dirty = 1;
#endif
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
r[0].dirty = 1;
r[1].dirty = 1;
};
struct arm920t_common *arm920t = target_to_arm920(target);
- struct arm *armv4_5;
if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{
return ERROR_TARGET_INVALID;
}
- armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
-
arm_arch_state(target);
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
state[arm920t->armv4_5_mmu.mmu_enabled],
static int arm920t_write_phys_memory(struct target *target,
uint32_t address, uint32_t size,
- uint32_t count, uint8_t *buffer)
+ uint32_t count, const uint8_t *buffer)
{
struct arm920t_common *arm920t = target_to_arm920(target);
/** Writes a buffer, in the specified word size, with current MMU settings. */
int arm920t_write_memory(struct target *target, uint32_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */
uint32_t C15_C_D_Ind, C15_C_I_Ind;
int i;
FILE *output;
- struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
int segment, index_t;
struct reg *r;
return retval;
}
- d_cache[segment][index_t].cam = regs[9];
-
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
for (i = 1; i < 9; i++)
{
- d_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
return retval;
}
- i_cache[segment][index_t].cam = regs[9];
-
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, "
for (i = 1; i < 9; i++)
{
- i_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
fclose(output);
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
/* force writeback of the valid data */
r = armv4_5->core_cache->reg_list;
fclose(output);
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
/* force writeback of the valid data */
r = armv4_5->core_cache->reg_list;