};
struct arm920t_common *arm920t = target_to_arm920(target);
- struct arm *armv4_5;
if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{
return ERROR_TARGET_INVALID;
}
- armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
-
arm_arch_state(target);
LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
state[arm920t->armv4_5_mmu.mmu_enabled],
uint32_t C15_C_D_Ind, C15_C_I_Ind;
int i;
FILE *output;
- struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
int segment, index_t;
struct reg *r;
if (CMD_ARGC != 1)
{
- command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
- return ERROR_OK;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
return retval;
}
- d_cache[segment][index_t].cam = regs[9];
-
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
for (i = 1; i < 9; i++)
{
- d_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
return retval;
}
- i_cache[segment][index_t].cam = regs[9];
-
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, "
for (i = 1; i < 9; i++)
{
- i_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
if (CMD_ARGC != 1)
{
- command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
- return ERROR_OK;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
}
else
{
- command_print(CMD_CTX,
- "usage: arm920t cp15i <opcode> [value] [address]");
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
return ERROR_OK;
.name = "cache_info",
.handler = arm920t_handle_cache_info_command,
.mode = COMMAND_EXEC,
+ .usage = "",
.help = "display information about target caches",
},
{
.name = "arm920t",
.mode = COMMAND_ANY,
.help = "arm920t command group",
+ .usage = "",
.chain = arm920t_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE