#endif
#include "arm920t.h"
-#include "time_support.h"
+#include <helper/time_support.h>
#include "target_type.h"
#include "register.h"
static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t* regs_p[1];
uint32_t regs[2];
uint32_t cp15c15 = 0x0;
+ struct reg *r = armv4_5->core_cache->reg_list;
/* load address into R1 */
regs[1] = address;
LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
+ r[0].dirty = 1;
+ r[1].dirty = 1;
return ERROR_OK;
}
uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
uint32_t cp15c15 = 0x0;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t regs[2];
+ struct reg *r = armv4_5->core_cache->reg_list;
/* load value, address into R0, R1 */
regs[0] = value;
LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
+ r[0].dirty = 1;
+ r[1].dirty = 1;
return ERROR_OK;
}
};
struct arm920t_common *arm920t = target_to_arm920(target);
- struct armv4_5_common_s *armv4_5;
+ struct arm *armv4_5;
if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+ buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm920t->armv4_5_mmu.mmu_enabled],
state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
target->state = TARGET_HALTED;
/* SVC, ARM state, IRQ and FIQ disabled */
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+ uint32_t cpsr;
+
+ cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+ cpsr &= ~0xff;
+ cpsr |= 0xd3;
+ arm_set_cpsr(armv4_5, cpsr);
+ armv4_5->cpsr->dirty = 1;
/* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
armv4_5->core_cache->reg_list[15].dirty = 1;
armv4_5->core_cache->reg_list[15].valid = 1;
- armv4_5->core_mode = ARMV4_5_MODE_SVC;
- armv4_5->core_state = ARMV4_5_STATE_ARM;
-
arm920t_disable_mmu_caches(target, 1, 1, 1);
arm920t->armv4_5_mmu.mmu_enabled = 0;
arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
return ERROR_OK;
}
+/* FIXME remove forward decls */
+static int arm920t_mrc(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t *value);
+static int arm920t_mcr(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t value);
+
int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
{
struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
+ arm7_9->armv4_5_common.mrc = arm920t_mrc;
+ arm7_9->armv4_5_common.mcr = arm920t_mcr;
+
/* initialize arm7/arm9 specific info (including armv4_5) */
arm9tdmi_init_arch_info(target, arm7_9, tap);
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
FILE *output;
struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
int segment, index;
+ struct reg *r;
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
if (retval != ERROR_OK)
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
- /* mark registers dirty. */
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
+ /* force writeback of the valid data */
+ r = armv4_5->core_cache->reg_list;
+ r[0].dirty = r[0].valid;
+ r[1].dirty = r[1].valid;
+ r[2].dirty = r[2].valid;
+ r[3].dirty = r[3].valid;
+ r[4].dirty = r[4].valid;
+ r[5].dirty = r[5].valid;
+ r[6].dirty = r[6].valid;
+ r[7].dirty = r[7].valid;
+
+ r = arm_reg_current(armv4_5, 8);
+ r->dirty = r->valid;
+
+ r = arm_reg_current(armv4_5, 9);
+ r->dirty = r->valid;
return ERROR_OK;
}
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
uint32_t Dlockdown, Ilockdown;
struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
int victim;
+ struct reg *r;
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
if (retval != ERROR_OK)
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
- /* mark registers dirty */
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
+ /* force writeback of the valid data */
+ r = armv4_5->core_cache->reg_list;
+ r[0].dirty = r[0].valid;
+ r[1].dirty = r[1].valid;
+ r[2].dirty = r[2].valid;
+ r[3].dirty = r[3].valid;
+ r[4].dirty = r[4].valid;
+ r[5].dirty = r[5].valid;
+ r[6].dirty = r[6].valid;
+ r[7].dirty = r[7].valid;
+
+ r = arm_reg_current(armv4_5, 8);
+ r->dirty = r->valid;
+
+ r = arm_reg_current(armv4_5, 9);
+ r->dirty = r->valid;
return ERROR_OK;
}
return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
}
-/** Registers commands to access coprocessor, cache, and MMU resources. */
-int arm920t_register_commands(struct command_context *cmd_ctx)
-{
- int retval;
- struct command *arm920t_cmd;
-
- retval = arm9tdmi_register_commands(cmd_ctx);
-
- arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t",
- NULL, COMMAND_ANY,
- "arm920t specific commands");
-
- register_command(cmd_ctx, arm920t_cmd, "cp15",
- arm920t_handle_cp15_command, COMMAND_EXEC,
- "display/modify cp15 register <num> [value]");
- register_command(cmd_ctx, arm920t_cmd, "cp15i",
- arm920t_handle_cp15i_command, COMMAND_EXEC,
- "display/modify cp15 (interpreted access) "
- "<opcode> [value] [address]");
- register_command(cmd_ctx, arm920t_cmd, "cache_info",
- arm920t_handle_cache_info_command, COMMAND_EXEC,
- "display information about target caches");
- register_command(cmd_ctx, arm920t_cmd, "read_cache",
- arm920t_handle_read_cache_command, COMMAND_EXEC,
- "display I/D cache content");
- register_command(cmd_ctx, arm920t_cmd, "read_mmu",
- arm920t_handle_read_mmu_command, COMMAND_EXEC,
- "display I/D mmu content");
-
- return retval;
-}
+static const struct command_registration arm920t_exec_command_handlers[] = {
+ {
+ .name = "cp15",
+ .handler = &arm920t_handle_cp15_command,
+ .mode = COMMAND_EXEC,
+ .help = "display/modify cp15 register",
+ .usage = "<num> [value]",
+ },
+ {
+ .name = "cp15i",
+ .handler = &arm920t_handle_cp15i_command,
+ .mode = COMMAND_EXEC,
+ .help = "display/modify cp15 (interpreted access)",
+ .usage = "<opcode> [value] [address]",
+ },
+ {
+ .name = "cache_info",
+ .handler = &arm920t_handle_cache_info_command,
+ .mode = COMMAND_EXEC,
+ .help = "display information about target caches",
+ },
+ {
+ .name = "read_cache",
+ .handler = &arm920t_handle_read_cache_command,
+ .mode = COMMAND_EXEC,
+ .help = "display I/D cache content",
+ },
+ {
+ .name = "read_mmu",
+ .handler = &arm920t_handle_read_mmu_command,
+ .mode = COMMAND_EXEC,
+ .help = "display I/D mmu content",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm920t_command_handlers[] = {
+ {
+ .chain = arm9tdmi_command_handlers,
+ },
+ {
+ .name = "arm920t",
+ .mode = COMMAND_ANY,
+ .help = "arm920t command group",
+ .chain = arm920t_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
/** Holds methods for ARM920 targets. */
struct target_type arm920t_target =
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
- .register_commands = arm920t_register_commands,
+ .commands = arm920t_command_handlers,
.target_create = arm920t_target_create,
.init_target = arm9tdmi_init_target,
.examine = arm7_9_examine,
- .mrc = arm920t_mrc,
- .mcr = arm920t_mcr,
};
projects / fw / openocd / blobdiff