+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
+ int retval;
jtag_info = &arm920t->arm7_9_common.jtag_info;
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 1;
uint8_t value_buf[4];
+ int retval;
jtag_info = &arm920t->arm7_9_common.jtag_info;
buf_set_u32(value_buf, 0, 32, value);
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
jtag_info = &arm920t->arm7_9_common.jtag_info;
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
}
// EXPORTED to FA256
-uint32_t arm920t_get_ttb(struct target *target)
+int arm920t_get_ttb(struct target *target, uint32_t *result)
{
int retval;
uint32_t ttb = 0x0;
0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
return retval;
- return ttb;
+ *result = ttb;
+ return ERROR_OK;
}
// EXPORTED to FA256
-void arm920t_disable_mmu_caches(struct target *target, int mmu,
+int arm920t_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
- jtag_execute_queue();
+ retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
cp15_control &= ~0x1U;
if (i_cache)
cp15_control &= ~0x1000U;
- arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+ retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+ return retval;
}
// EXPORTED to FA256
-void arm920t_enable_mmu_caches(struct target *target, int mmu,
+int arm920t_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
- jtag_execute_queue();
+ retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
cp15_control |= 0x1U;
if (i_cache)
cp15_control |= 0x1000U;
- arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+ retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+ return retval;
}
// EXPORTED to FA256
-void arm920t_post_debug_entry(struct target *target)
+int arm920t_post_debug_entry(struct target *target)
{
uint32_t cp15c15;
struct arm920t_common *arm920t = target_to_arm920(target);
+ int retval;
/* examine cp15 control reg */
- arm920t_read_cp15_physical(target,
+ retval = arm920t_read_cp15_physical(target,
CP15PHYS_CTRL, &arm920t->cp15_control_reg);
- jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
uint32_t cache_type_reg;
/* identify caches */
- arm920t_read_cp15_physical(target,
+ retval = arm920t_read_cp15_physical(target,
CP15PHYS_CACHETYPE, &cache_type_reg);
- jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
armv4_5_identify_cache(cache_type_reg,
&arm920t->armv4_5_mmu.armv4_5_cache);
}
/* save i/d fault status and address register */
/* FIXME use opcode macros */
- arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
- arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
- arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
- arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+ retval = arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32,
{
/* read-modify-write CP15 test state register
* to disable I/D-cache linefills */
- arm920t_read_cp15_physical(target,
+ retval = arm920t_read_cp15_physical(target,
CP15PHYS_TESTSTATE, &cp15c15);
- jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
cp15c15 |= 0x600;
- arm920t_write_cp15_physical(target,
+ retval = arm920t_write_cp15_physical(target,
CP15PHYS_TESTSTATE, cp15c15);
+ if (retval != ERROR_OK)
+ return retval;
}
+ return ERROR_OK;
}
// EXPORTED to FA256
static int arm920_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys)
{
- int type;
uint32_t cb;
- int domain;
- uint32_t ap;
struct arm920t_common *arm920t = target_to_arm920(target);
- uint32_t ret = armv4_5_mmu_translate_va(target,
- &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap);
- if (type == -1)
- {
- return ret;
- }
+ uint32_t ret;
+ int retval = armv4_5_mmu_translate_va(target,
+ &arm920t->armv4_5_mmu, virt, &cb, &ret);
+ if (retval != ERROR_OK)
+ return retval;
*phys = ret;
return ERROR_OK;
}
* in memory marked read only
* by MMU
*/
- int type;
uint32_t cb;
- int domain;
- uint32_t ap;
uint32_t pa;
/*
* We need physical address and cb
*/
- pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
- address, &type, &cb, &domain, &ap);
- if (type == -1)
- return pa;
+ retval = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
+ address, &cb, &pa);
+ if (retval != ERROR_OK)
+ return retval;
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
}
}
- return retval;
+ return ERROR_OK;
}
// EXPORTED to FA256
uint32_t CRn, uint32_t CRm,
uint32_t value);
-int arm920t_init_arch_info(struct target *target,
+static int arm920t_init_arch_info(struct target *target,
struct arm920t_common *arm920t, struct jtag_tap *tap)
{
struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
int i;
FILE *output;
struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
- int segment, index;
+ int segment, index_t;
struct reg *r;
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
arm920t_write_cp15_physical(target,
CP15PHYS_TESTSTATE, cp15c15);
- for (index = 0; index < 64; index++)
+ for (index_t = 0; index_t < 64; index_t++)
{
/* Ra:
* r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
*/
- regs[0] = 0x0 | (segment << 5) | (index << 26);
+ regs[0] = 0x0 | (segment << 5) | (index_t << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
return retval;
}
- d_cache[segment][index].cam = regs[9];
+ d_cache[segment][index_t].cam = regs[9];
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
PRIx32 ", content (%s):\n",
- segment, index, regs[9],
+ segment, index_t, regs[9],
(regs[9] & 0x10) ? "valid" : "invalid");
for (i = 1; i < 9; i++)
{
- d_cache[segment][index].data[i] = regs[i];
+ d_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
arm920t_write_cp15_physical(target,
CP15PHYS_TESTSTATE, cp15c15);
- for (index = 0; index < 64; index++)
+ for (index_t = 0; index_t < 64; index_t++)
{
/* Ra:
* r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
*/
- regs[0] = 0x0 | (segment << 5) | (index << 26);
+ regs[0] = 0x0 | (segment << 5) | (index_t << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
return retval;
}
- i_cache[segment][index].cam = regs[9];
+ i_cache[segment][index_t].cam = regs[9];
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, "
"CAM: 0x%8.8" PRIx32 ", content (%s):\n",
- segment, index, regs[9],
+ segment, index_t, regs[9],
(regs[9] & 0x10) ? "valid" : "invalid");
for (i = 1; i < 9; i++)
{
- i_cache[segment][index].data[i] = regs[i];
+ i_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
projects / fw / openocd / blobdiff