mips: mips32_pracc_exec error propagation fixes

[fw/openocd] / src / target / arm920t.c

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index a80a37810dba79e08b89f9f1e677887a1ba1a070..a3a5adf1592bebfc5c226dd00694cf9371adc153 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -89,11 +89,16 @@ static int arm920t_read_cp15_physical(struct target *target,
        uint8_t access_type_buf = 1;
        uint8_t reg_addr_buf = reg_addr & 0x3f;
        uint8_t nr_w_buf = 0;
+       int retval;
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 1;
        fields[0].out_value = &access_type_buf;
@@ -137,13 +142,18 @@ static int arm920t_write_cp15_physical(struct target *target,
        uint8_t reg_addr_buf = reg_addr & 0x3f;
        uint8_t nr_w_buf = 1;
        uint8_t value_buf[4];
+       int retval;
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
        buf_set_u32(value_buf, 0, 32, value);
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 1;
        fields[0].out_value = &access_type_buf;
@@ -191,8 +201,12 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 
@@ -267,7 +281,10 @@ static int arm920t_read_cp15_interpreted(struct target *target,
 #endif
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -309,7 +326,10 @@ int arm920t_write_cp15_interpreted(struct target *target,
 #endif
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -389,24 +409,33 @@ int arm920t_enable_mmu_caches(struct target *target, int mmu,
 }
 
 // EXPORTED to FA256
-void arm920t_post_debug_entry(struct target *target)
+int arm920t_post_debug_entry(struct target *target)
 {
        uint32_t cp15c15;
        struct arm920t_common *arm920t = target_to_arm920(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm920t_read_cp15_physical(target,
+       retval = arm920t_read_cp15_physical(target,
                        CP15PHYS_CTRL, &arm920t->cp15_control_reg);
-       jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
 
        if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
                uint32_t cache_type_reg;
                /* identify caches */
-               arm920t_read_cp15_physical(target,
+               retval = arm920t_read_cp15_physical(target,
                                CP15PHYS_CACHETYPE, &cache_type_reg);
-               jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                armv4_5_identify_cache(cache_type_reg,
                                &arm920t->armv4_5_mmu.armv4_5_cache);
        }
@@ -420,10 +449,18 @@ void arm920t_post_debug_entry(struct target *target)
 
        /* save i/d fault status and address register */
                        /* FIXME use opcode macros */
-       arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
-       arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
-       arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
-       arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+       retval = arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+       if (retval != ERROR_OK)
+               return retval;
 
        LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
                ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32,
@@ -433,13 +470,20 @@ void arm920t_post_debug_entry(struct target *target)
        {
                /* read-modify-write CP15 test state register
                 * to disable I/D-cache linefills */
-               arm920t_read_cp15_physical(target,
+               retval = arm920t_read_cp15_physical(target,
                                CP15PHYS_TESTSTATE, &cp15c15);
-               jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                cp15c15 |= 0x600;
-               arm920t_write_cp15_physical(target,
+               retval = arm920t_write_cp15_physical(target,
                                CP15PHYS_TESTSTATE, cp15c15);
+               if (retval != ERROR_OK)
+                       return retval;
        }
+       return ERROR_OK;
 }
 
 // EXPORTED to FA256
@@ -1116,7 +1160,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        fclose(output);
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
        r = armv4_5->core_cache->reg_list;
@@ -1443,7 +1490,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        fclose(output);
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
        r = armv4_5->core_cache->reg_list;