&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
scan_field_t fields[2];
- u8 databus[4];
- u8 breakpoint;
+ uint8_t databus[4];
+ uint8_t breakpoint;
- jtag_add_end_state(TAP_DRPAUSE);
+ jtag_set_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1;
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
- jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_DRPAUSE));
+ jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE));
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
fields[1].in_value = NULL;
fields[1].out_value = databus;
- jtag_add_dr_scan(2, fields, jtag_add_end_state(TAP_DRPAUSE));
+ jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE));
if (breakpoint & 1)
target->debug_reason = DBG_REASON_WATCHPOINT;
}
static int arm7tdmi_num_bits[]={1, 32};
-static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
+static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint)
{
- u32 values[2]={breakpoint, flip_u32(out, 32)};
+ uint32_t values[2]={breakpoint, flip_u32(out, 32)};
jtag_add_dr_out(jtag_info->tap,
2,
}
/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
-static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
+static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t out, uint32_t *deprecated, int breakpoint)
{
- jtag_add_end_state(TAP_DRPAUSE);
+ jtag_set_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
}
/* clock the target, reading the databus */
-int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
+int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
{
int retval = ERROR_OK;
scan_field_t fields[2];
- jtag_add_end_state(TAP_DRPAUSE);
+ jtag_set_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
- fields[1].in_value = (u8 *)in;
+ fields[1].in_value = (uint8_t *)in;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
- jtag_add_callback(arm7flip32, (u8 *)in);
+ jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
jtag_add_runtest(0, jtag_get_end_state());
return ERROR_OK;
}
-void arm_endianness(u8 *tmp, void *in, int size, int be, int flip)
+void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
{
- u32 readback=le_to_h_u32(tmp);
+ uint32_t readback=le_to_h_u32(tmp);
if (flip)
readback=flip_u32(readback, 32);
switch (size)
case 4:
if (be)
{
- h_u32_to_be(((u8*)in), readback);
+ h_u32_to_be(((uint8_t*)in), readback);
} else
{
- h_u32_to_le(((u8*)in), readback);
+ h_u32_to_le(((uint8_t*)in), readback);
}
break;
case 2:
if (be)
{
- h_u16_to_be(((u8*)in), readback & 0xffff);
+ h_u16_to_be(((uint8_t*)in), readback & 0xffff);
} else
{
- h_u16_to_le(((u8*)in), readback & 0xffff);
+ h_u16_to_le(((uint8_t*)in), readback & 0xffff);
}
break;
case 1:
- *((u8 *)in)= readback & 0xff;
+ *((uint8_t *)in)= readback & 0xff;
break;
}
}
-static int arm7endianness(u8 *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
+static int arm7endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
{
- arm_endianness((u8 *)captured, in, (int)size, (int)be, 1);
+ uint8_t *in=(uint8_t *)arg;
+ arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1);
return ERROR_OK;
}
int retval = ERROR_OK;
scan_field_t fields[2];
- jtag_add_end_state(TAP_DRPAUSE);
+ jtag_set_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
- jtag_add_callback4(arm7endianness, in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
+ jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
jtag_add_runtest(0, jtag_get_end_state());
if (in)
{
- LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
+ LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
}
else
{
return ERROR_OK;
}
-void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
+void arm7tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
* The solution is to arrange for a large out/in scan in this loop and
* and convert data afterwards.
*/
-void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
+void arm7tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
{
int i;
/* get pointers to arch-specific information */
}
}
-void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
+void arm7tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
{
int i;
/* get pointers to arch-specific information */
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
- u32 *buf_u32 = buffer;
- u16 *buf_u16 = buffer;
- u8 *buf_u8 = buffer;
+ uint32_t *buf_u32 = buffer;
+ uint16_t *buf_u16 = buffer;
+ uint8_t *buf_u8 = buffer;
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
}
}
-void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
+void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7tdmi_clock_data_in(jtag_info, xpsr);
}
-void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
+void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+ LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
/* MSR1 fetched */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
}
-void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
+void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
}
-void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
+void arm7tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
{
int i;
/* get pointers to arch-specific information */
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
}
-void arm7tdmi_load_word_regs(target_t *target, u32 mask)
+void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
}
-void arm7tdmi_store_word_regs(target_t *target, u32 mask)
+void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
}
-void arm7tdmi_write_pc(target_t *target, u32 pc)
+void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
projects / fw / openocd / blobdiff