armv4_5_common_t -> struct arm

[fw/openocd] / src / target / arm7_9_common.h

diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index fc2c3201a46b9b887fe1693ef4a3f85e5dca07ae..41858c6840f83bd64025e8ddf5667ecf2569c264 100644 (file)
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -30,46 +30,46 @@
 #define ARM7_9_COMMON_H
 
 #include "breakpoints.h"
-#include "etm.h"
+#include "armv4_5.h"
 
 #define        ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
 
 /**
  * Structure for items that are common between both ARM7 and ARM9 targets.
  */
-typedef struct arm7_9_common_s
+struct arm7_9_common
 {
+       struct arm armv4_5_common;
        uint32_t common_magic;
 
-       arm_jtag_t jtag_info; /**< JTAG information for target */
-       reg_cache_t *eice_cache; /**< Embedded ICE register cache */
+       struct arm_jtag jtag_info; /**< JTAG information for target */
+       struct reg_cache *eice_cache; /**< Embedded ICE register cache */
 
        uint32_t arm_bkpt; /**< ARM breakpoint instruction */
        uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
+
        int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
+       int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
        int breakpoint_count; /**< Current number of set breakpoints */
        int wp_available; /**< Current number of available watchpoint units */
        int wp_available_max; /**< Maximum number of available watchpoint units */
        int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
        int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
        int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
-       int force_hw_bkpts;
        int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
-       int use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
-       int need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
-
-       etm_context_t *etm_ctx;
+       bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
+       bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
 
-       int has_single_step;
-       int has_monitor_mode;
-       int has_vector_catch; /**< Specifies if the target has a reset vector catch */
+       bool has_single_step;
+       bool has_monitor_mode;
+       bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
 
-       int debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
+       bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
 
-       struct working_area_s *dcc_working_area;
+       bool fast_memory_access;
+       bool dcc_downloads;
 
-       int fast_memory_access;
-       int dcc_downloads;
+       struct working_area *dcc_working_area;
 
        int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
 
@@ -100,16 +100,20 @@ typedef struct arm7_9_common_s
 
        void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
 
-       void (*pre_debug_entry)(target_t *target); /**< Callback function called before entering debug mode */
        void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */
 
        void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
        void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
 
-       armv4_5_common_t armv4_5_common;
-       void *arch_info;
 
-} arm7_9_common_t;
+};
+
+static inline struct arm7_9_common *
+target_to_arm7_9(struct target_s *target)
+{
+       return container_of(target->arch_info, struct arm7_9_common,
+                       armv4_5_common);
+}
 
 int arm7_9_register_commands(struct command_context_s *cmd_ctx);
 
@@ -137,19 +141,19 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
 int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
 int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
 
-int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, uint32_t entry_point, void *arch_info);
+int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
 
-int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
+int arm7_9_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
+int arm7_9_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
+int arm7_9_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint);
+int arm7_9_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint);
 
 void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc);
 void arm7_9_disable_eice_step(target_t *target);
 
 int arm7_9_execute_sys_speed(struct target_s *target);
 
-int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
+int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9);
+int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p);
 
 #endif /* ARM7_9_COMMON_H */