* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007,2008 Øyvind Harboe *
+ * Copyright (C) 2007-2009 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2008 by Spencer Oliver *
* Copyright (C) 2008 by Hongtao Zheng *
* hontor@126.com *
* *
+ * Copyright (C) 2009 by David Brownell *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include "embeddedice.h"
#include "target_request.h"
#include "etm.h"
-#include "time_support.h"
+#include <helper/time_support.h>
#include "arm_simulator.h"
+#include "arm_semihosting.h"
#include "algorithm.h"
#include "register.h"
+#include "armv4_5.h"
/**
* @param target Pointer to an ARM7/9 target to setup
* @return Result of clearing the watchpoints on the target
*/
-int arm7_9_setup(struct target *target)
+static int arm7_9_setup(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
return retval;
}
+ current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr);
if (current_instr == arm7_9->arm_bkpt)
if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if (arm7_9->breakpoint_count == 0)
{
/* make sure we don't have any dangling breakpoints. This is vital upon
* @return Error status if watchpoint set fails or the result of executing the
* JTAG queue
*/
-int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
+static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @return Error status while trying to unset the watchpoint or the result of
* executing the JTAG queue
*/
-int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
+static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if (arm7_9->wp_available < 1)
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
- jtag_set_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL);
+ arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL);
+ arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
long long then = timeval_ms();
int timeout;
* @param target Pointer to the target to issue commands to
* @return Always ERROR_OK
*/
-int arm7_9_execute_fast_sys_speed(struct target *target)
+static int arm7_9_execute_fast_sys_speed(struct target *target)
{
static int set = 0;
static uint8_t check_value[4], check_mask[4];
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
- jtag_set_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL);
+ arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL);
+ arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
if (!set)
{
* @return ERROR_OK unless there are issues with the JTAG queue or when reading
* from the Embedded ICE unit
*/
-int arm7_9_handle_target_request(void *priv)
+static int arm7_9_handle_target_request(void *priv)
{
int retval = ERROR_OK;
struct target *target = priv;
}
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
- int check_pc = 0;
- if (target->state == TARGET_RESET)
- {
- if (target->reset_halt)
- {
- enum reset_types jtag_reset_config = jtag_get_reset_config();
- if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
- {
- check_pc = 1;
- }
- }
- }
-
target->state = TARGET_HALTED;
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
- if (check_pc)
- {
- struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
- uint32_t t=*((uint32_t *)reg->value);
- if (t != 0)
- {
- LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
- }
- }
+ if (arm_semihosting(target, &retval) != 0)
+ return retval;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
int arm7_9_assert_reset(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+ bool use_event = false;
LOG_DEBUG("target->state: %s",
target_state_name(target));
- enum reset_types jtag_reset_config = jtag_get_reset_config();
- if (!(jtag_reset_config & RESET_HAS_SRST))
- {
- LOG_ERROR("Can't assert SRST");
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
+ use_event = true;
+ else if (!(jtag_reset_config & RESET_HAS_SRST)) {
+ LOG_ERROR("%s: how to reset?", target_name(target));
return ERROR_FAIL;
}
*/
bool srst_asserted = false;
- if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
+ if (!use_event
+ && !(jtag_reset_config & RESET_SRST_PULLS_TRST)
&& (jtag_reset_config & RESET_SRST_NO_GATING))
{
jtag_add_reset(0, 1);
if (target->reset_halt)
{
/*
- * Some targets do not support communication while SRST is asserted. We need to
- * set up the reset vector catch here.
+ * For targets that don't support communication while SRST is
+ * asserted, we need to set up the reset vector catch first.
*
- * If TRST is asserted, then these settings will be reset anyway, so setting them
- * here is harmless.
+ * When we use TRST+SRST and that's equivalent to a power-up
+ * reset, these settings may well be reset anyway; so setting
+ * them here won't matter.
*/
if (arm7_9->has_vector_catch)
{
- /* program vector catch register to catch reset vector */
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+ /* program vector catch register to catch reset */
+ embeddedice_write_reg(&arm7_9->eice_cache
+ ->reg_list[EICE_VEC_CATCH], 0x1);
- /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
- jtag_add_runtest(1, jtag_get_end_state());
+ /* extra runtest added as issues were found with
+ * certain ARM9 cores (maybe more) - AT91SAM9260
+ * and STR9
+ */
+ jtag_add_runtest(1, TAP_IDLE);
}
else
{
- /* program watchpoint unit to match on reset vector address */
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
+ /* program watchpoint unit to match on reset vector
+ * address
+ */
+ embeddedice_write_reg(&arm7_9->eice_cache
+ ->reg_list[EICE_W0_ADDR_VALUE], 0x0);
+ embeddedice_write_reg(&arm7_9->eice_cache
+ ->reg_list[EICE_W0_ADDR_MASK], 0x3);
+ embeddedice_write_reg(&arm7_9->eice_cache
+ ->reg_list[EICE_W0_DATA_MASK],
+ 0xffffffff);
+ embeddedice_write_reg(&arm7_9->eice_cache
+ ->reg_list[EICE_W0_CONTROL_VALUE],
+ EICE_W_CTRL_ENABLE);
+ embeddedice_write_reg(&arm7_9->eice_cache
+ ->reg_list[EICE_W0_CONTROL_MASK],
+ ~EICE_W_CTRL_nOPC & 0xff);
}
}
- /* here we should issue an SRST only, but we may have to assert TRST as well */
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
- {
- jtag_add_reset(1, 1);
- } else if (!srst_asserted)
- {
- jtag_add_reset(0, 1);
+ if (use_event) {
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ } else {
+ /* If we use SRST ... we'd like to issue just SRST, but the
+ * board or chip may be set up so we have to assert TRST as
+ * well. On some chips that combination is equivalent to a
+ * power-up reset, and generally clobbers EICE state.
+ */
+ if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+ jtag_add_reset(1, 1);
+ else if (!srst_asserted)
+ jtag_add_reset(0, 1);
+ jtag_add_sleep(50000);
}
target->state = TARGET_RESET;
- jtag_add_sleep(50000);
+ register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
- armv4_5_invalidate_core_regs(target);
-
- if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
+ /* REVISIT why isn't standard debug entry logic sufficient?? */
+ if (target->reset_halt
+ && (!(jtag_reset_config & RESET_SRST_PULLS_TRST)
+ || use_event))
{
- /* debug entry was already prepared in arm7_9_assert_reset() */
+ /* debug entry was prepared above */
target->debug_reason = DBG_REASON_DBGRQ;
}
* @param target Pointer to the ARM7/9 target to have halt cleared
* @return Always ERROR_OK
*/
-int arm7_9_clear_halt(struct target *target)
+static int arm7_9_clear_halt(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int arm7_9_soft_reset_halt(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
uint32_t r0_thumb, pc_thumb;
LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
/* Entered debug from Thumb mode */
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
+ armv4_5->core_state = ARM_STATE_THUMB;
arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
}
+ /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
+
/* all register content is now invalid */
- if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
- {
- return retval;
- }
+ register_cache_invalidate(armv4_5->core_cache);
/* SVC, ARM state, IRQ and FIQ disabled */
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+ uint32_t cpsr;
- /* start fetching from 0x0 */
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_cache->reg_list[15].valid = 1;
+ cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+ cpsr &= ~0xff;
+ cpsr |= 0xd3;
+ arm_set_cpsr(armv4_5, cpsr);
+ armv4_5->cpsr->dirty = 1;
- armv4_5->core_mode = ARMV4_5_MODE_SVC;
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ /* start fetching from 0x0 */
+ buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
+ armv4_5->pc->dirty = 1;
+ armv4_5->pc->valid = 1;
/* reset registers */
for (i = 0; i <= 14; i++)
{
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
+ struct reg *r = arm_reg_current(armv4_5, i);
+
+ buf_set_u32(r->value, 0, 32, 0xffffffff);
+ r->dirty = 1;
+ r->valid = 1;
}
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
uint32_t context[16];
uint32_t* context_p[16];
uint32_t r0_thumb, pc_thumb;
- uint32_t cpsr;
+ uint32_t cpsr, cpsr_mask = 0;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
{
LOG_DEBUG("target entered debug from Thumb state");
/* Entered debug from Thumb mode */
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
+ armv4_5->core_state = ARM_STATE_THUMB;
+ cpsr_mask = 1 << 5;
arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
- LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
- }
- else
- {
+ LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
+ ", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
+ } else if (buf_get_u32(dbg_stat->value, 5, 1)) {
+ /* \todo Get some vaguely correct handling of Jazelle, if
+ * anyone ever uses it and full info becomes available.
+ * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
+ * B.7.3 for the reverse. That'd be the bare minimum...
+ */
+ LOG_DEBUG("target entered debug from Jazelle state");
+ armv4_5->core_state = ARM_STATE_JAZELLE;
+ cpsr_mask = 1 << 24;
+ LOG_ERROR("Jazelle debug entry -- BROKEN!");
+ } else {
LOG_DEBUG("target entered debug from ARM state");
/* Entered debug from ARM mode */
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ armv4_5->core_state = ARM_STATE_ARM;
}
for (i = 0; i < 16; i++)
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- /* if the core has been executing in Thumb state, set the T bit */
- if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
- cpsr |= 0x20;
-
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
-
- armv4_5->core_mode = cpsr & 0x1f;
+ /* Sync our CPSR copy with J or T bits EICE reported, but
+ * which we then erased by putting the core into ARM mode.
+ */
+ arm_set_cpsr(armv4_5, cpsr | cpsr_mask);
if (!is_arm_mode(armv4_5->core_mode))
{
LOG_DEBUG("target entered debug state in %s mode",
arm_mode_name(armv4_5->core_mode));
- if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ if (armv4_5->core_state == ARM_STATE_THUMB)
{
LOG_DEBUG("thumb state, applying fixups");
context[0] = r0_thumb;
context[15] = pc_thumb;
- } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ } else if (armv4_5->core_state == ARM_STATE_ARM)
{
/* adjust value stored by STM */
context[15] -= 3 * 4;
}
if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
- context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+ context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
else
- context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+ context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
for (i = 0; i <= 15; i++)
{
+ struct reg *r = arm_reg_current(armv4_5, i);
+
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
+
+ buf_set_u32(r->value, 0, 32, context[i]);
+ /* r0 and r15 (pc) have to be restored later */
+ r->dirty = (i == 0) || (i == 15);
+ r->valid = 1;
}
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
/* exceptions other than USR & SYS have a saved program status register */
- if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
- {
+ if (armv4_5->spsr) {
uint32_t spsr;
arm7_9->read_xpsr(target, &spsr, 1);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
+ buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
+ armv4_5->spsr->dirty = 0;
+ armv4_5->spsr->valid = 1;
}
- /* r0 and r15 (pc) have to be restored later */
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
-
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
if (arm7_9->post_debug_entry)
- arm7_9->post_debug_entry(target);
+ {
+ retval = arm7_9->post_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
return ERROR_OK;
}
* @return Error if the target is not halted, has an invalid core mode, or if
* the JTAG queue fails to execute
*/
-int arm7_9_full_context(struct target *target)
+static int arm7_9_full_context(struct target *target)
{
int i;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
LOG_DEBUG("-");
uint32_t tmp_cpsr;
/* change processor mode (and mask T bit) */
- tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+ tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
+ & 0xe0;
tmp_cpsr |= armv4_5_number_to_mode(i);
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
}
/* restore processor mode (mask T bit) */
- arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+ arm7_9->write_xpsr_im8(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
+ 0, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
* @return Error status if the target is not halted or the core mode in the
* armv4_5 struct is invalid.
*/
-int arm7_9_restore_context(struct target *target)
+static int arm7_9_restore_context(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *reg;
- struct armv4_5_core_reg *reg_arch_info;
- enum armv4_5_mode current_mode = armv4_5->core_mode;
+ struct arm_reg *reg_arch_info;
+ enum arm_mode current_mode = armv4_5->core_mode;
int i, j;
int dirty;
int mode_change;
{
dirty = 1;
LOG_DEBUG("examining dirty reg: %s", reg->name);
- if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
+ if ((reg_arch_info->mode != ARM_MODE_ANY)
&& (reg_arch_info->mode != current_mode)
- && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
- && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
+ && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
+ && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
{
mode_change = 1;
LOG_DEBUG("require mode change");
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
- tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+ tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
+ 0, 8) & 0xe0;
tmp_cpsr |= armv4_5_number_to_mode(i);
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
reg_arch_info = reg->arch_info;
- if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
+ if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
{
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
}
}
- if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
+ if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
{
/* restore processor mode (mask T bit) */
uint32_t tmp_cpsr;
- tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+ tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
tmp_cpsr |= armv4_5_number_to_mode(i);
tmp_cpsr &= ~0x20;
LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
}
- else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
+ else if (armv4_5->cpsr->dirty)
{
/* CPSR has been changed, full restore necessary (mask T bit) */
- LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
- arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
+ arm7_9->write_xpsr(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32)
+ & ~0x20, 0);
+ armv4_5->cpsr->dirty = 0;
+ armv4_5->cpsr->valid = 1;
}
/* restore PC */
- LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
- arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
- armv4_5->core_cache->reg_list[15].dirty = 0;
-
- if (arm7_9->post_restore_context)
- arm7_9->post_restore_context(target);
+ LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ arm7_9->write_pc(target, buf_get_u32(armv4_5->pc->value, 0, 32));
+ armv4_5->pc->dirty = 0;
return ERROR_OK;
}
* @param target Pointer to the ARM7/9 target to be restarted
* @return Result of executing the JTAG queue
*/
-int arm7_9_restart_core(struct target *target)
+static int arm7_9_restart_core(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
- jtag_set_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL);
+ arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL);
+ arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
- jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
+ jtag_add_runtest(1, TAP_IDLE);
return jtag_execute_queue();
}
*
* @param target Pointer to the ARM7/9 target to enable watchpoints on
*/
-void arm7_9_enable_watchpoints(struct target *target)
+static void arm7_9_enable_watchpoints(struct target *target)
{
struct watchpoint *watchpoint = target->watchpoints;
*
* @param target Pointer to the ARM7/9 target to enable breakpoints on
*/
-void arm7_9_enable_breakpoints(struct target *target)
+static void arm7_9_enable_breakpoints(struct target *target)
{
struct breakpoint *breakpoint = target->breakpoints;
int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err, retval = ERROR_OK;
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+ buf_set_u32(armv4_5->pc->value, 0, 32, address);
uint32_t current_pc;
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
- if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
+ breakpoint = breakpoint_find(target,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
+ if (breakpoint != NULL)
{
LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
return retval;
}
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ if (armv4_5->core_state == ARM_STATE_ARM)
arm7_9->branch_resume(target);
- else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ else if (armv4_5->core_state == ARM_STATE_THUMB)
{
arm7_9->branch_resume_thumb(target);
}
return err;
}
- arm7_9_debug_entry(target);
- LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ retval = arm7_9_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->pc->value, 0, 32));
LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
return retval;
}
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ if (armv4_5->core_state == ARM_STATE_ARM)
{
arm7_9->branch_resume(target);
}
- else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ else if (armv4_5->core_state == ARM_STATE_THUMB)
{
arm7_9->branch_resume_thumb(target);
}
if (!debug_execution)
{
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
target->state = TARGET_RUNNING;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t current_pc;
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
if (next_pc != current_pc)
{
int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = NULL;
int err, retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+ buf_set_u32(armv4_5->pc->value, 0, 32, address);
- uint32_t current_pc;
- current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+ uint32_t current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
- if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
- if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
- {
- return retval;
- }
+ breakpoint = breakpoint_find(target, current_pc);
+ if (breakpoint != NULL) {
+ retval = arm7_9_unset_breakpoint(target, breakpoint);
+ if (retval != ERROR_OK)
+ return retval;
+ }
target->debug_reason = DBG_REASON_SINGLESTEP;
arm7_9->enable_single_step(target, next_pc);
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ if (armv4_5->core_state == ARM_STATE_ARM)
{
arm7_9->branch_resume(target);
}
- else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ else if (armv4_5->core_state == ARM_STATE_THUMB)
{
arm7_9->branch_resume_thumb(target);
}
arm7_9->disable_single_step(target);
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
if (err != ERROR_OK)
{
target->state = TARGET_UNKNOWN;
} else {
- arm7_9_debug_entry(target);
+ retval = arm7_9_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
return err;
}
-int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
+static int arm7_9_read_core_reg(struct target *target, struct reg *r,
+ int num, enum arm_mode mode)
{
uint32_t* reg_p[16];
uint32_t value;
int retval;
+ struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
-
- enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
-
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (reg_mode != ARMV4_5_MODE_ANY))
+ && (areg->mode != ARM_MODE_ANY))
{
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
- tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+ tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
tmp_cpsr |= mode;
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
/* read a program status register
* if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
*/
- struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
- int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
-
- arm7_9->read_xpsr(target, &value, spsr);
+ arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
}
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
+ r->valid = 1;
+ r->dirty = 0;
+ buf_set_u32(r->value, 0, 32, value);
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (reg_mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
- arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+ arm7_9->write_xpsr_im8(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 8)
+ & ~0x20, 0, 0);
}
return ERROR_OK;
}
-int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value)
+static int arm7_9_write_core_reg(struct target *target, struct reg *r,
+ int num, enum arm_mode mode, uint32_t value)
{
uint32_t reg[16];
+ struct arm_reg *areg = r->arch_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
-
- enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
-
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (reg_mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
- tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+ tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
tmp_cpsr |= mode;
tmp_cpsr &= ~0x20;
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
/* write a program status register
* if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
*/
- struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
- int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
+ int spsr = (areg->mode != ARM_MODE_ANY);
/* if we're writing the CPSR, mask the T bit */
if (!spsr)
arm7_9->write_xpsr(target, value, spsr);
}
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+ r->valid = 1;
+ r->dirty = 0;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (reg_mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
- arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+ arm7_9->write_xpsr_im8(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 8)
+ & ~0x20, 0, 0);
}
return jtag_execute_queue();
int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
uint32_t reg[16];
uint32_t num_accesses = 0;
int thisrun_accesses;
}
}
break;
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
- break;
}
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
- for (i = 0; i <= last_reg; i++)
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
+ for (i = 0; i <= last_reg; i++) {
+ struct reg *r = arm_reg_current(armv4_5, i);
+
+ r->dirty = r->valid;
+ }
arm7_9->read_xpsr(target, &cpsr, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
- arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+ arm7_9->write_xpsr_im8(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 8)
+ & ~0x20, 0, 0);
return ERROR_TARGET_DATA_ABORT;
}
int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
uint32_t reg[16];
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
+ {
retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
+ {
retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
- retval = arm7_9_execute_sys_speed(target);
+ {
+ retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
num_accesses += thisrun_accesses;
}
break;
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
- break;
}
/* Re-Set DBGACK */
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
- for (i = 0; i <= last_reg; i++)
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
+ for (i = 0; i <= last_reg; i++) {
+ struct reg *r = arm_reg_current(armv4_5, i);
+
+ r->dirty = r->valid;
+ }
arm7_9->read_xpsr(target, &cpsr, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
- arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+ arm7_9->write_xpsr_im8(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 8)
+ & ~0x20, 0, 0);
return ERROR_TARGET_DATA_ABORT;
}
0xeafffff9 /* b w */
};
-int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
-
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
}
}
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct reg_param reg_params[1];
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
- armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
+ armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
dcc_count = count;
dcc_buffer = buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
- arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
+ arm7_9->dcc_working_area->address,
+ arm7_9->dcc_working_area->address + 6*4,
+ 20*1000, &armv4_5_info, arm7_9_dcc_completion);
if (retval == ERROR_OK)
{
}
-COMMAND_HANDLER(handle_arm7_9_write_xpsr_command)
+int arm7_9_check_reset(struct target *target)
{
- uint32_t value;
- int spsr;
- int retval;
- struct target *target = get_current_target(CMD_CTX);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- if (!is_arm7_9(arm7_9))
+ if (get_target_reset_nag() && !arm7_9->dcc_downloads)
{
- command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
- return ERROR_TARGET_INVALID;
+ LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
}
- if (target->state != TARGET_HALTED)
+ if (get_target_reset_nag() && (target->working_area_size == 0))
{
- command_print(CMD_CTX, "can't write registers while running");
- return ERROR_FAIL;
+ LOG_WARNING("NOTE! Severe performance degradation without working memory enabled.");
}
- if (CMD_ARGC < 2)
+ if (get_target_reset_nag() && !arm7_9->fast_memory_access)
{
- command_print(CMD_CTX, "usage: write_xpsr <value> <not cpsr | spsr>");
- return ERROR_FAIL;
- }
-
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], spsr);
-
- /* if we're writing the CPSR, mask the T bit */
- if (!spsr)
- value &= ~0x20;
-
- arm7_9->write_xpsr(target, value, spsr);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- LOG_ERROR("JTAG error while writing to xpsr");
- return retval;
+ LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.");
}
return ERROR_OK;
}
-COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command)
+COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
{
- uint32_t value;
- int rotate;
- int spsr;
- int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return ERROR_TARGET_INVALID;
}
- if (target->state != TARGET_HALTED)
- {
- command_print(CMD_CTX, "can't write registers while running");
- return ERROR_FAIL;
- }
-
- if (CMD_ARGC < 3)
- {
- command_print(CMD_CTX, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
- return ERROR_FAIL;
- }
-
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], rotate);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], spsr);
+ if (CMD_ARGC > 0)
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
- arm7_9->write_xpsr_im8(target, value, rotate, spsr);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
- return retval;
- }
+ command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
return ERROR_OK;
}
-COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
-{
- uint32_t value;
- uint32_t mode;
- int num;
- struct target *target = get_current_target(CMD_CTX);
- struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-
- if (!is_arm7_9(arm7_9))
- {
- command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
- return ERROR_TARGET_INVALID;
- }
-
- if (target->state != TARGET_HALTED)
- {
- command_print(CMD_CTX, "can't write registers while running");
- return ERROR_FAIL;
- }
-
- if (CMD_ARGC < 3)
- {
- command_print(CMD_CTX, "usage: write_core_reg <num> <mode> <value>");
- return ERROR_FAIL;
- }
-
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], num);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], mode);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
-
- return arm7_9_write_core_reg(target, num, mode, value);
-}
-
-COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
+COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
{
struct target *target = get_current_target(CMD_CTX);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
if (CMD_ARGC > 0)
- COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
- command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
+ command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
return ERROR_OK;
}
-COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
+COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
{
struct target *target = get_current_target(CMD_CTX);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
if (CMD_ARGC > 0)
- COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
- command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
+ command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
return ERROR_OK;
}
-COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
+static int arm7_9_setup_semihosting(struct target *target, int enable)
{
- struct target *target = get_current_target(CMD_CTX);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (!is_arm7_9(arm7_9))
{
- command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+ LOG_USER("current target isn't an ARM7/ARM9 target");
return ERROR_TARGET_INVALID;
}
- if (CMD_ARGC > 0)
- COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
+ if (arm7_9->has_vector_catch) {
+ struct reg *vector_catch = &arm7_9->eice_cache
+ ->reg_list[EICE_VEC_CATCH];
- command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
+ if (!vector_catch->valid)
+ embeddedice_read_reg(vector_catch);
+ buf_set_u32(vector_catch->value, 2, 1, enable);
+ embeddedice_store_reg(vector_catch);
+ } else {
+ /* TODO: allow optional high vectors and/or BKPT_HARD */
+ if (enable)
+ breakpoint_add(target, 8, 4, BKPT_SOFT);
+ else
+ breakpoint_remove(target, 8);
+ }
return ERROR_OK;
}
armv4_5->read_core_reg = arm7_9_read_core_reg;
armv4_5->write_core_reg = arm7_9_write_core_reg;
armv4_5->full_context = arm7_9_full_context;
+ armv4_5->setup_semihosting = arm7_9_setup_semihosting;
- if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+ retval = arm_init_arch_info(target, armv4_5);
+ if (retval != ERROR_OK)
return retval;
return target_register_timer_callback(arm7_9_handle_target_request,
1, 1, target);
}
-int arm7_9_register_commands(struct command_context *cmd_ctx)
-{
- struct command *arm7_9_cmd;
-
- arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
- NULL, COMMAND_ANY, "arm7/9 specific commands");
-
- register_command(cmd_ctx, arm7_9_cmd, "write_xpsr",
- handle_arm7_9_write_xpsr_command, COMMAND_EXEC,
- "write program status register <value> <not cpsr | spsr>");
- register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8",
- handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC,
- "write program status register "
- "<8bit immediate> <rotate> <not cpsr | spsr>");
-
- register_command(cmd_ctx, arm7_9_cmd, "write_core_reg",
- handle_arm7_9_write_core_reg_command, COMMAND_EXEC,
- "write core register <num> <mode> <value>");
-
- register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
- handle_arm7_9_dbgrq_command, COMMAND_ANY,
- "use EmbeddedICE dbgrq instead of breakpoint "
- "for target halt requests <enable | disable>");
- register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access",
- handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
- "use fast memory accesses instead of slower "
- "but potentially safer accesses <enable | disable>");
- register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads",
- handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
- "use DCC downloads for larger memory writes <enable | disable>");
-
- armv4_5_register_commands(cmd_ctx);
-
- etm_register_commands(cmd_ctx);
-
- return ERROR_OK;
-}
+static const struct command_registration arm7_9_any_command_handlers[] = {
+ {
+ "dbgrq",
+ .handler = handle_arm7_9_dbgrq_command,
+ .mode = COMMAND_ANY,
+ .usage = "['enable'|'disable']",
+ .help = "use EmbeddedICE dbgrq instead of breakpoint "
+ "for target halt requests",
+ },
+ {
+ "fast_memory_access",
+ .handler = handle_arm7_9_fast_memory_access_command,
+ .mode = COMMAND_ANY,
+ .usage = "['enable'|'disable']",
+ .help = "use fast memory accesses instead of slower "
+ "but potentially safer accesses",
+ },
+ {
+ "dcc_downloads",
+ .handler = handle_arm7_9_dcc_downloads_command,
+ .mode = COMMAND_ANY,
+ .usage = "['enable'|'disable']",
+ .help = "use DCC downloads for larger memory writes",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm7_9_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .chain = etm_command_handlers,
+ },
+ {
+ .name = "arm7_9",
+ .mode = COMMAND_ANY,
+ .help = "arm7/9 specific commands",
+ .chain = arm7_9_any_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
projects / fw / openocd / blobdiff