{
if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
{
- WARNING("srst resets test logic, too");
retval = jtag_add_reset(1, 1);
}
}
{
if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
{
- WARNING("srst resets test logic, too");
retval = jtag_add_reset(1, 1);
}
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int i;
+ int retval;
- if (target->state == TARGET_RUNNING)
- {
- target->type->halt(target);
- }
+ if ((retval=target->type->halt(target))!=ERROR_OK)
+ return retval;
- while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+ for (i=0; i<10; i++)
{
+ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
+ break;
embeddedice_read_reg(dbg_stat);
- jtag_execute_queue();
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ /* do not eat all CPU, time out after 1 se*/
+ usleep(100*1000);
+
+ }
+ if (i==10)
+ {
+ ERROR("Failed to halt CPU after 1 sec");
+ return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
- return ERROR_TARGET_ALREADY_HALTED;
+ return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
- if ((retval = jtag->execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
if (arm7_9->post_debug_entry)
arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
- for (i = 0; i < count; i++)
+ int little=target->endianness==TARGET_LITTLE_ENDIAN;
+ if (count>2)
{
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
- buffer += 4;
+ /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+ core function repeated.
+ */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer+=4;
+
+ embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+ u8 reg_addr = ice_reg->addr & 0x1f;
+ int chain_pos = ice_reg->jtag_info->chain_pos;
+ /* we want the compiler to duplicate the code, which it does not
+ * do automatically.
+ */
+ if (little)
+ {
+ for (i = 1; i < count - 1; i++)
+ {
+ embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+ } else
+ {
+ for (i = 1; i < count - 1; i++)
+ {
+ embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+ }
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ } else
+ {
+ for (i = 0; i < count; i++)
+ {
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
}
target->type->halt(target);