{
dirty = 1;
LOG_DEBUG("examining dirty reg: %s", reg->name);
- if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
+ if ((reg_arch_info->mode != ARM_MODE_ANY)
&& (reg_arch_info->mode != current_mode)
- && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
- && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
+ && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
+ && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
{
mode_change = 1;
LOG_DEBUG("require mode change");
reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
reg_arch_info = reg->arch_info;
- if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
+ if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
{
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY))
+ && (areg->mode != ARM_MODE_ANY))
{
uint32_t tmp_cpsr;
/* read a program status register
* if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
*/
- arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
+ arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
r->dirty = 0;
buf_set_u32(r->value, 0, 32, value);
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
/* write a program status register
* if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
*/
- int spsr = (areg->mode != ARMV4_5_MODE_ANY);
+ int spsr = (areg->mode != ARM_MODE_ANY);
/* if we're writing the CPSR, mask the T bit */
if (!spsr)
r->valid = 1;
r->dirty = 0;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
struct reg_param reg_params[1];
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);