arm7_9_enable_sw_bkpts(target);
}
- arm7_9->reinit_embeddedice = 0;
-
return ERROR_OK;
}
-int arm7_9_jtag_callback(enum jtag_event event, void *priv)
+/* set things up after a reset / on startup */
+int arm7_9_setup(target_t *target)
{
- target_t *target = priv;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
- /* a test-logic reset occured
+ /* a test-logic reset have occured
* the EmbeddedICE registers have been reset
* hardware breakpoints have been cleared
*/
- if (event == JTAG_TRST_ASSERTED)
- {
- arm7_9->reinit_embeddedice = 1;
- }
-
- return ERROR_OK;
+ return arm7_9_reinit_embeddedice(target);
}
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
int arm7_9_handle_target_request(void *priv)
{
target_t *target = priv;
+ if (!target->type->examined)
+ return ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
+
if (!target->dbg_msg_enabled)
return ERROR_OK;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- if (arm7_9->reinit_embeddedice)
- {
- arm7_9_reinit_embeddedice(target);
- }
-
/* read debug status register */
embeddedice_read_reg(dbg_stat);
if ((retval = jtag_execute_queue()) != ERROR_OK)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
{
- LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
+/* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32)); */
if (target->state == TARGET_UNKNOWN)
{
target->state = TARGET_RUNNING;
return ERROR_OK;
}
+/*
+ Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
+ in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
+ while the core is held in reset(SRST). It isn't possible to program the halt
+ condition once reset was asserted, hence a hook that allows the target to set
+ up its reset-halt condition prior to asserting reset.
+*/
+
int arm7_9_assert_reset(target_t *target)
{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (!(jtag_reset_config & RESET_HAS_SRST))
return ERROR_FAIL;
}
- /* we can't know what state the target is in as we might e.g.
- * be resetting after a power dropout, so we need to issue a tms/srst
- */
-
- /* assert SRST and TRST */
- /* system would get ouf sync if we didn't reset test-logic, too */
- jtag_add_reset(1, 1);
-
- jtag_add_sleep(5000);
+ if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
+ {
+ /*
+ * Some targets do not support communication while SRST is asserted. We need to
+ * set up the reset vector catch here.
+ *
+ * If TRST is asserted, then these settings will be reset anyway, so setting them
+ * here is harmless.
+ */
+ if (arm7_9->has_vector_catch)
+ {
+ /* program vector catch register to catch reset vector */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+ }
+ else
+ {
+ /* program watchpoint unit to match on reset vector address */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+ }
+ }
/* here we should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- /* at this point we TRST *may* be deasserted */
- arm7_9_prepare_reset_halt(target);
-
-
armv4_5_invalidate_core_regs(target);
return ERROR_OK;
int i;
int retval;
- if ((retval=target->type->halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target))!=ERROR_OK)
return retval;
for (i=0; i<10; i++)
return ERROR_OK;
}
-int arm7_9_prepare_reset_halt(target_t *target)
-{
- if ((target->reset_mode!=RESET_HALT)&&(target->reset_mode!=RESET_INIT))
- {
- return ERROR_OK;
- }
- return arm7_9_halt(target);
-}
-
int arm7_9_halt(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
if (target->state == TARGET_HALTED)
{
- LOG_WARNING("target was already halted");
+ LOG_DEBUG("target was already halted");
return ERROR_OK;
}
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
}
+ else
+ {
+ /* we came here in a reset_halt or reset_init sequence
+ * debug entry was already prepared in arm7_9_prepare_reset_halt()
+ */
+ target->debug_reason = DBG_REASON_DBGRQ;
+
+ return ERROR_OK;
+ }
}
if (arm7_9->use_dbgrq)
}
}
- target->type->halt(target);
+ target_halt(target);
for (i=0; i<100; i++)
{
- target->type->poll(target);
+ target_poll(target);
if (target->state == TARGET_HALTED)
break;
usleep(1000); /* sleep 1ms */
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
arm7_9->has_monitor_mode = 0;
arm7_9->has_vector_catch = 0;
- arm7_9->reinit_embeddedice = 0;
-
arm7_9->debug_entry_from_reset = 0;
arm7_9->dcc_working_area = NULL;
- arm7_9->fast_memory_access = 0;
- arm7_9->dcc_downloads = 0;
-
- jtag_register_event_callback(arm7_9_jtag_callback, target);
+ arm7_9->fast_memory_access = fast_and_dangerous;
+ arm7_9->dcc_downloads = fast_and_dangerous;
armv4_5->arch_info = arm7_9;
armv4_5->read_core_reg = arm7_9_read_core_reg;
projects / fw / openocd / blobdiff