* shadowed registers, and support for the Thumb instruction set.
*
* Processor differences include things like presence or absence of MMU
- * and cache, pipeline sizes, use of a modified Harvard Architecure
- * (with separate instruction and data busses from the CPU), support
+ * and cache, pipeline sizes, use of a modified Harvard Architecture
+ * (with separate instruction and data buses from the CPU), support
* for cpu clock gating during idle, and more.
*/
} else
LOG_ERROR("BUG: no hardware comparator available");
- LOG_DEBUG("BPID: %" PRId32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %d",
+ LOG_DEBUG("BPID: %" PRIu32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->set);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
- LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
+ LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->type);
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR,
+ LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR,
breakpoint->unique_id,
breakpoint->address);
}
if (breakpoint->type == BKPT_HARD) {
- LOG_DEBUG("BPID: %" PRId32 " Releasing hw wp: %d",
+ LOG_DEBUG("BPID: %" PRIu32 " Releasing hw wp: %d",
breakpoint->unique_id,
breakpoint->set);
if (breakpoint->set == 1) {
/**
* Clears the halt condition for an ARM7/9 target. If it isn't coming out of
- * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
+ * reset and if DBGRQ is used, it is programmed to be deasserted. If the reset
* vector catch was used, it is restored. Otherwise, the control value is
* restored and the watchpoint unit is restored if it was in use.
*
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *arm = &arm7_9->arm;
+ struct {
+ uint32_t value;
+ uint8_t *reg_p;
+ } read_cache[6 * (16 + 1)];
+ int read_cache_idx = 0;
LOG_DEBUG("-");
for (j = 0; j < 15; j++) {
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i), j).valid) {
- reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(
+ read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(
arm->core_cache,
armv4_5_number_to_mode(i),
j).value;
+ reg_p[j] = &read_cache[read_cache_idx].value;
+ read_cache_idx++;
mask |= 1 << j;
ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i),
/* check if the PSR has to be read */
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
16).valid) {
- arm7_9->read_xpsr(target,
- (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
- armv4_5_number_to_mode(i), 16).value, 1);
+ read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(arm->core_cache,
+ armv4_5_number_to_mode(i), 16).value;
+ arm7_9->read_xpsr(target, &read_cache[read_cache_idx].value, 1);
+ read_cache_idx++;
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
16).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
+ /*
+ * FIXME: regs in cache should be tagged as 'valid' only now,
+ * not before the jtag_execute_queue()
+ */
+ while (read_cache_idx) {
+ read_cache_idx--;
+ buf_set_u32(read_cache[read_cache_idx].reg_p, 0, 32, read_cache[read_cache_idx].value);
+ }
return ERROR_OK;
}
breakpoint = breakpoint_find(target,
buf_get_u32(arm->pc->value, 0, 32));
if (breakpoint != NULL) {
- LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRId32,
+ LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRIu32,
breakpoint->address,
breakpoint->unique_id);
retval = arm7_9_unset_breakpoint(target, breakpoint);