dsp5680xx - mark erase after unlocking flash

[fw/openocd] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 3bbe8b07ad27c30fac93152e2ef8b31f8d446d2c..5fbcd4dee23c3684916bff82e2b2b9b149482203 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007-2009 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -392,6 +392,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
                        {
                                return retval;
                        }
+                       current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
                        if (current_instr == arm7_9->thumb_bkpt)
                                if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
                                {
@@ -1518,7 +1519,10 @@ static int arm7_9_full_context(struct target *target)
        }
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
         * SYS shares registers with User, so we don't touch SYS
@@ -1603,7 +1607,6 @@ static int arm7_9_restore_context(struct target *target)
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm *armv4_5 = &arm7_9->armv4_5_common;
        struct reg *reg;
-       struct arm_reg *reg_arch_info;
        enum arm_mode current_mode = armv4_5->core_mode;
        int i, j;
        int dirty;
@@ -1621,7 +1624,10 @@ static int arm7_9_restore_context(struct target *target)
                arm7_9->pre_restore_context(target);
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
         * SYS shares registers with User, so we don't touch SYS
@@ -1637,13 +1643,14 @@ static int arm7_9_restore_context(struct target *target)
                for (j = 0; j <= 16; j++)
                {
                        reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
-                       reg_arch_info = reg->arch_info;
                        if (reg->dirty == 1)
                        {
                                if (reg->valid == 1)
                                {
                                        dirty = 1;
                                        LOG_DEBUG("examining dirty reg: %s", reg->name);
+                                       struct arm_reg *reg_arch_info;
+                                       reg_arch_info = reg->arch_info;
                                        if ((reg_arch_info->mode != ARM_MODE_ANY)
                                                && (reg_arch_info->mode != current_mode)
                                                && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
@@ -1682,8 +1689,6 @@ static int arm7_9_restore_context(struct target *target)
                        for (j = 0; j <= 14; j++)
                        {
                                reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
-                               reg_arch_info = reg->arch_info;
-
 
                                if (reg->dirty == 1)
                                {
@@ -1705,6 +1710,7 @@ static int arm7_9_restore_context(struct target *target)
                        }
 
                        reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
+                       struct arm_reg *reg_arch_info;
                        reg_arch_info = reg->arch_info;
                        if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
                        {
@@ -1816,7 +1822,6 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm *armv4_5 = &arm7_9->armv4_5_common;
-       struct breakpoint *breakpoint = target->breakpoints;
        struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
        int err, retval = ERROR_OK;
 
@@ -1843,6 +1848,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
        /* the front-end may request us not to handle breakpoints */
        if (handle_breakpoints)
        {
+               struct breakpoint *breakpoint;
                breakpoint = breakpoint_find(target,
                                buf_get_u32(armv4_5->pc->value, 0, 32));
                if (breakpoint != NULL)
@@ -2128,7 +2134,6 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
                int num, enum arm_mode mode)
 {
        uint32_t* reg_p[16];
-       uint32_t value;
        int retval;
        struct arm_reg *areg = r->arch_info;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -2152,6 +2157,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
        }
 
+       uint32_t value = 0;
        if ((num >= 0) && (num <= 15))
        {
                /* read a normal core register */
@@ -2425,7 +2431,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
        return ERROR_OK;
 }
 
-int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm *armv4_5 = &arm7_9->armv4_5_common;
@@ -2649,7 +2655,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 }
 
 static int dcc_count;
-static uint8_t *dcc_buffer;
+static const uint8_t *dcc_buffer;
 
 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
@@ -2661,7 +2667,7 @@ static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int
 
        int little = target->endianness == TARGET_LITTLE_ENDIAN;
        int count = dcc_count;
-       uint8_t *buffer = dcc_buffer;
+       const uint8_t *buffer = dcc_buffer;
        if (count > 2)
        {
                /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
@@ -2714,7 +2720,7 @@ static const uint32_t dcc_code[] =
        0xeafffff9      /*    b   w                   */
 };
 
-int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);