- adds two speeds to jtag_speed. reset and post reset speed. Default

[fw/openocd] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index dd713b9b9f4b0aaa012f2c294b1f9077e967344a..5ce1db5671d50d254448c9826fcd74382a73143b 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -860,16 +860,26 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
        int i;
+       int retval;
        
-       if (target->state == TARGET_RUNNING)
-       {
-               target->type->halt(target);
-       }
+       if ((retval=target->type->halt(target))!=ERROR_OK)
+               return retval;
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+       for (i=0; i<10; i++)
        {
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
+                       break;
                embeddedice_read_reg(dbg_stat);
-               jtag_execute_queue();
+               if ((retval=jtag_execute_queue())!=ERROR_OK)
+                       return retval;
+               /* do not eat all CPU, time out after 1 se*/
+               usleep(100*1000);
+               
+       }
+       if (i==10)
+       {
+               ERROR("Failed to halt CPU after 1 sec");
+               return ERROR_TARGET_TIMEOUT;
        }
        target->state = TARGET_HALTED;
        
@@ -962,7 +972,7 @@ int arm7_9_halt(target_t *target)
        if (target->state == TARGET_HALTED)
        {
                WARNING("target was already halted");
-               return ERROR_TARGET_ALREADY_HALTED;
+               return ERROR_OK;
        }
        
        if (target->state == TARGET_UNKNOWN)
@@ -1159,7 +1169,7 @@ int arm7_9_debug_entry(target_t *target)
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
 
-       if ((retval = jtag->execute_queue()) != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
                return retval;
 
        if (arm7_9->post_debug_entry)
@@ -1743,7 +1753,6 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
 {
        u32 reg[16];
-       int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
@@ -1795,14 +1804,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
                arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
        }
        
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
-               ERROR("JTAG failure");
-               exit(-1);
-       }
-       
-       return ERROR_OK;
-       
+       return jtag_execute_queue();
 }
 
 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
@@ -2165,16 +2167,60 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 
        arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
        
-       for (i = 0; i < count; i++)
+       int little=target->endianness==TARGET_LITTLE_ENDIAN;
+       if (count>2)
        {
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
-               buffer += 4;
+               /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+                  core function repeated. 
+                */
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+               buffer+=4;
+               
+               embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+               u8 reg_addr = ice_reg->addr & 0x1f;
+               int chain_pos = ice_reg->jtag_info->chain_pos;
+               /* we want the compiler to duplicate the code, which it does not
+                * do automatically.
+                */
+               if (little)
+               {
+                       for (i = 1; i < count - 1; i++)
+                       {
+                               embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+                               buffer += 4;
+                       }
+               } else
+               {
+                       for (i = 1; i < count - 1; i++)
+                       {
+                               embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+                               buffer += 4;
+                       }
+               }
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+       } else
+       {
+               for (i = 0; i < count; i++)
+               {
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+                       buffer += 4;
+               }
        }
        
        target->type->halt(target);
        
-       while (target->state != TARGET_HALTED)
+       for (i=0; i<100; i++)
+       {
                target->type->poll(target);
+               if (target->state == TARGET_HALTED)
+                       break;
+               usleep(1000); /* sleep 1ms */
+       }
+       if (i == 100)
+       {
+               ERROR("bulk write timed out, target not halted");
+               return ERROR_TARGET_TIMEOUT;
+       }
        
        /* restore target state */
        buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
@@ -2334,7 +2380,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                ERROR("JTAG error while writing to xpsr");
-               exit(-1);
+               return retval;
        }
        
        return ERROR_OK;
@@ -2376,7 +2422,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                ERROR("JTAG error while writing 8-bit immediate to xpsr");
-               exit(-1);
+               return retval;
        }
        
        return ERROR_OK;