#include "etm.h"
#include <helper/time_support.h>
#include "arm_simulator.h"
+#include "arm_semihosting.h"
#include "algorithm.h"
#include "register.h"
+#include "armv4_5.h"
/**
}
}
+ if (arm_semihosting(target, &retval) != 0)
+ return retval;
+
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
uint32_t r0_thumb, pc_thumb;
LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
/* Entered debug from Thumb mode */
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
+ armv4_5->core_state = ARM_STATE_THUMB;
arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
}
{
LOG_DEBUG("target entered debug from Thumb state");
/* Entered debug from Thumb mode */
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
+ armv4_5->core_state = ARM_STATE_THUMB;
cpsr_mask = 1 << 5;
arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
* B.7.3 for the reverse. That'd be the bare minimum...
*/
LOG_DEBUG("target entered debug from Jazelle state");
- armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+ armv4_5->core_state = ARM_STATE_JAZELLE;
cpsr_mask = 1 << 24;
LOG_ERROR("Jazelle debug entry -- BROKEN!");
} else {
LOG_DEBUG("target entered debug from ARM state");
/* Entered debug from ARM mode */
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ armv4_5->core_state = ARM_STATE_ARM;
}
for (i = 0; i < 16; i++)
LOG_DEBUG("target entered debug state in %s mode",
arm_mode_name(armv4_5->core_mode));
- if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ if (armv4_5->core_state == ARM_STATE_THUMB)
{
LOG_DEBUG("thumb state, applying fixups");
context[0] = r0_thumb;
context[15] = pc_thumb;
- } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ } else if (armv4_5->core_state == ARM_STATE_ARM)
{
/* adjust value stored by STM */
context[15] -= 3 * 4;
}
if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
- context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+ context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
else
- context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+ context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
for (i = 0; i <= 15; i++)
{
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *reg;
struct arm_reg *reg_arch_info;
- enum armv4_5_mode current_mode = armv4_5->core_mode;
+ enum arm_mode current_mode = armv4_5->core_mode;
int i, j;
int dirty;
int mode_change;
{
dirty = 1;
LOG_DEBUG("examining dirty reg: %s", reg->name);
- if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
+ if ((reg_arch_info->mode != ARM_MODE_ANY)
&& (reg_arch_info->mode != current_mode)
- && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
- && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
+ && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
+ && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
{
mode_change = 1;
LOG_DEBUG("require mode change");
reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
reg_arch_info = reg->arch_info;
- if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
+ if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
{
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
return retval;
}
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ if (armv4_5->core_state == ARM_STATE_ARM)
arm7_9->branch_resume(target);
- else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ else if (armv4_5->core_state == ARM_STATE_THUMB)
{
arm7_9->branch_resume_thumb(target);
}
return retval;
}
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ if (armv4_5->core_state == ARM_STATE_ARM)
{
arm7_9->branch_resume(target);
}
- else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ else if (armv4_5->core_state == ARM_STATE_THUMB)
{
arm7_9->branch_resume_thumb(target);
}
arm7_9->enable_single_step(target, next_pc);
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ if (armv4_5->core_state == ARM_STATE_ARM)
{
arm7_9->branch_resume(target);
}
- else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ else if (armv4_5->core_state == ARM_STATE_THUMB)
{
arm7_9->branch_resume_thumb(target);
}
}
static int arm7_9_read_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode)
+ int num, enum arm_mode mode)
{
uint32_t* reg_p[16];
uint32_t value;
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY))
+ && (areg->mode != ARM_MODE_ANY))
{
uint32_t tmp_cpsr;
/* read a program status register
* if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
*/
- arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
+ arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
r->dirty = 0;
buf_set_u32(r->value, 0, 32, value);
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
}
static int arm7_9_write_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode, uint32_t value)
+ int num, enum arm_mode mode, uint32_t value)
{
uint32_t reg[16];
struct arm_reg *areg = r->arch_info;
if ((num < 0) || (num > 16))
return ERROR_INVALID_ARGUMENTS;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
uint32_t tmp_cpsr;
/* change processor mode (mask T bit) */
/* write a program status register
* if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
*/
- int spsr = (areg->mode != ARMV4_5_MODE_ANY);
+ int spsr = (areg->mode != ARM_MODE_ANY);
/* if we're writing the CPSR, mask the T bit */
if (!spsr)
r->valid = 1;
r->dirty = 0;
- if ((mode != ARMV4_5_MODE_ANY)
+ if ((mode != ARM_MODE_ANY)
&& (mode != armv4_5->core_mode)
- && (areg->mode != ARMV4_5_MODE_ANY)) {
+ && (areg->mode != ARM_MODE_ANY)) {
/* restore processor mode (mask T bit) */
arm7_9->write_xpsr_im8(target,
buf_get_u32(armv4_5->cpsr->value, 0, 8)
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
return ERROR_TARGET_DATA_ABORT;
}
- if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+ if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
{
LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
0xeafffff9 /* b w */
};
-extern int armv4_5_run_algorithm_inner(struct target *target,
- int num_mem_params, struct mem_param *mem_params,
- int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
- int timeout_ms, void *arch_info,
- int (*run_it)(struct target *target, uint32_t exit_point,
- int timeout_ms, void *arch_info));
-
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
}
}
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct reg_param reg_params[1];
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
- armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
+ armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
return ERROR_OK;
}
+COMMAND_HANDLER(handle_arm7_9_semihosting_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+ if (!is_arm7_9(arm7_9))
+ {
+ command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+ return ERROR_TARGET_INVALID;
+ }
+
+ if (CMD_ARGC > 0)
+ {
+ int semihosting;
+
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+ if (arm7_9->has_vector_catch) {
+ struct reg *vector_catch = &arm7_9->eice_cache
+ ->reg_list[EICE_VEC_CATCH];
+
+ if (!vector_catch->valid)
+ embeddedice_read_reg(vector_catch);
+ buf_set_u32(vector_catch->value, 2, 1, semihosting);
+ embeddedice_store_reg(vector_catch);
+ } else {
+ /* TODO: allow optional high vectors and/or BKPT_HARD */
+ if (semihosting)
+ breakpoint_add(target, 8, 4, BKPT_SOFT);
+ else
+ breakpoint_remove(target, 8);
+ }
+
+ /* FIXME never let that "catch" be dropped! */
+ arm7_9->armv4_5_common.is_semihosting = semihosting;
+
+ }
+
+ command_print(CMD_CTX, "semihosting is %s",
+ arm7_9->armv4_5_common.is_semihosting
+ ? "enabled" : "disabled");
+
+ return ERROR_OK;
+}
+
int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
{
int retval = ERROR_OK;
armv4_5->write_core_reg = arm7_9_write_core_reg;
armv4_5->full_context = arm7_9_full_context;
- if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+ retval = arm_init_arch_info(target, armv4_5);
+ if (retval != ERROR_OK)
return retval;
return target_register_timer_callback(arm7_9_handle_target_request,
.usage = "<enable | disable>",
.help = "use DCC downloads for larger memory writes",
},
+ {
+ "semihosting",
+ .handler = &handle_arm7_9_semihosting_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<enable | disable>",
+ .help = "activate support for semihosting operations",
+ },
COMMAND_REGISTRATION_DONE
};
const struct command_registration arm7_9_command_handlers[] = {
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