reg_t -> struct reg

[fw/openocd] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 65f26875438f824923b93297f4086a70fd609441..0523d82979368fc0ef654963a0258bb485a14194 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -66,7 +66,7 @@ static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
  * @param arm7_9 Pointer to the common struct for an ARM7/9 target
  * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
  */
-static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, breakpoint_t *breakpoint)
+static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
 {
        if (!arm7_9->wp0_used)
        {
@@ -178,7 +178,7 @@ int arm7_9_setup(target_t *target)
  *                 targets
  * @return ERROR_OK if successful
  */
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p)
+int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
@@ -210,7 +210,7 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, str
  *         queue.  For software breakpoints, this will be the status of the
  *         required memory reads and writes
  */
-int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        int retval = ERROR_OK;
@@ -339,7 +339,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  *         queue.  For software breakpoints, this will be the status of the
  *         required memory reads and writes
  */
-int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
 {
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -434,7 +434,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  * @return An error status if there is a problem adding the breakpoint or the
  *         result of setting the breakpoint
  */
-int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
@@ -484,7 +484,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  * @return Error status if there was a problem unsetting the breakpoint or the
  *         watchpoints could not be cleared
  */
-int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int arm7_9_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
 {
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -520,7 +520,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  * @return Error status if watchpoint set fails or the result of executing the
  *         JTAG queue
  */
-int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -591,7 +591,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  * @return Error status while trying to unset the watchpoint or the result of
  *         executing the JTAG queue
  */
-int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -639,7 +639,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  * @param watchpoint Pointer to the watchpoint to be added
  * @return Error status while trying to add the watchpoint
  */
-int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
@@ -672,7 +672,7 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  * @param watchpoint Pointer to the watchpoint to be removed
  * @return Result of trying to unset the watchpoint
  */
-int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+int arm7_9_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
 {
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -704,7 +704,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* set RESTART instruction */
        jtag_set_end_state(TAP_IDLE);
@@ -757,7 +757,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* set RESTART instruction */
        jtag_set_end_state(TAP_IDLE);
@@ -834,7 +834,7 @@ int arm7_9_handle_target_request(void *priv)
                return ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
+       struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
@@ -891,7 +891,7 @@ int arm7_9_poll(target_t *target)
 {
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* read debug status register */
        embeddedice_read_reg(dbg_stat);
@@ -931,7 +931,7 @@ int arm7_9_poll(target_t *target)
 
                        if (check_pc)
                        {
-                               reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
+                               struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
                                uint32_t t=*((uint32_t *)reg->value);
                                if (t != 0)
                                {
@@ -1115,7 +1115,7 @@ int arm7_9_deassert_reset(target_t *target)
 int arm7_9_clear_halt(target_t *target)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        /* we used DBGRQ only if we didn't come out of reset */
        if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
@@ -1173,8 +1173,8 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
        int i;
        int retval;
 
@@ -1291,7 +1291,7 @@ int arm7_9_halt(target_t *target)
        }
 
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        LOG_DEBUG("target->state: %s",
                  target_state_name(target));
@@ -1354,8 +1354,8 @@ int arm7_9_debug_entry(target_t *target)
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 #ifdef _DEBUG_ARM7_9_
        LOG_DEBUG("-");
@@ -1599,8 +1599,8 @@ int arm7_9_restore_context(target_t *target)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *reg;
-       armv4_5_core_reg_t *reg_arch_info;
+       struct reg *reg;
+       struct armv4_5_core_reg *reg_arch_info;
        enum armv4_5_mode current_mode = armv4_5->core_mode;
        int i, j;
        int dirty;
@@ -1770,7 +1770,7 @@ int arm7_9_restart_core(struct target_s *target)
  */
 void arm7_9_enable_watchpoints(struct target_s *target)
 {
-       watchpoint_t *watchpoint = target->watchpoints;
+       struct watchpoint *watchpoint = target->watchpoints;
 
        while (watchpoint)
        {
@@ -1788,7 +1788,7 @@ void arm7_9_enable_watchpoints(struct target_s *target)
  */
 void arm7_9_enable_breakpoints(struct target_s *target)
 {
-       breakpoint_t *breakpoint = target->breakpoints;
+       struct breakpoint *breakpoint = target->breakpoints;
 
        /* set any pending breakpoints */
        while (breakpoint)
@@ -1802,8 +1802,8 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       breakpoint_t *breakpoint = target->breakpoints;
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct breakpoint *breakpoint = target->breakpoints;
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
        int err, retval = ERROR_OK;
 
        LOG_DEBUG("-");
@@ -2014,7 +2014,7 @@ int arm7_9_step(struct target_s *target, int current, uint32_t address, int hand
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       breakpoint_t *breakpoint = NULL;
+       struct breakpoint *breakpoint = NULL;
        int err, retval;
 
        if (target->state != TARGET_HALTED)
@@ -2114,7 +2114,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
+       enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
 
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
@@ -2144,7 +2144,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
                /* read a program status register
                 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
                 */
-               armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
+               struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
                int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
 
                arm7_9->read_xpsr(target, &value, spsr);
@@ -2178,7 +2178,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
+       enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
 
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
@@ -2207,7 +2207,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
                /* write a program status register
                * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
                */
-               armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
+               struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
                int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
 
                /* if we're writing the CPSR, mask the T bit */
@@ -2409,7 +2409,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        uint32_t reg[16];
        uint32_t num_accesses = 0;
@@ -2609,7 +2609,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
                buffer += 4;
 
-               embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+               struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
                uint8_t reg_addr = ice_reg->addr & 0x1f;
                struct jtag_tap *tap;
                tap = ice_reg->jtag_info->tap;
@@ -2690,7 +2690,7 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
                }
        }
 
-       armv4_5_algorithm_t armv4_5_info;
+       struct armv4_5_algorithm armv4_5_info;
        struct reg_param reg_params[1];
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
@@ -2723,8 +2723,8 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
 
 int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
 {
-       working_area_t *crc_algorithm;
-       armv4_5_algorithm_t armv4_5_info;
+       struct working_area *crc_algorithm;
+       struct armv4_5_algorithm armv4_5_info;
        struct reg_param reg_params[2];
        int retval;
 
@@ -2807,9 +2807,9 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
 
 int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
 {
-       working_area_t *erase_check_algorithm;
+       struct working_area *erase_check_algorithm;
        struct reg_param reg_params[3];
-       armv4_5_algorithm_t armv4_5_info;
+       struct armv4_5_algorithm armv4_5_info;
        int retval;
        uint32_t i;
 
@@ -2877,7 +2877,7 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_command)
        int spsr;
        int retval;
        target_t *target = get_current_target(cmd_ctx);
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
 
        if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
@@ -2922,7 +2922,7 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command)
        int spsr;
        int retval;
        target_t *target = get_current_target(cmd_ctx);
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
 
        if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
@@ -2963,7 +2963,7 @@ COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
        uint32_t mode;
        int num;
        target_t *target = get_current_target(cmd_ctx);
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
 
        if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
@@ -2994,7 +2994,7 @@ COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 {
        target_t *target = get_current_target(cmd_ctx);
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
 
        if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
@@ -3027,7 +3027,7 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
 {
        target_t *target = get_current_target(cmd_ctx);
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
 
        if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
@@ -3060,7 +3060,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
 {
        target_t *target = get_current_target(cmd_ctx);
-       armv4_5_common_t *armv4_5;
+       struct arm *armv4_5;
        struct arm7_9_common *arm7_9;
 
        if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
@@ -3093,7 +3093,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
 int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9)
 {
        int retval = ERROR_OK;
-       armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *armv4_5 = &arm7_9->armv4_5_common;
 
        arm7_9->common_magic = ARM7_9_COMMON_MAGIC;