#include "arm720t.h"
#include "jtag.h"
#include "log.h"
+#include "time_support.h"
#include <stdlib.h>
#include <string.h>
/* forward declarations */
int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int arm720t_quit();
-int arm720t_arch_state(struct target_s *target, char *buf, int buf_size);
+int arm720t_quit(void);
+int arm720t_arch_state(struct target_s *target);
int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm720t_soft_reset_halt(struct target_s *target);
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm720t_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm720t_read_memory,
.write_memory = arm720t_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
-
+ .checksum_memory = arm7_9_checksum_memory,
+ .blank_check_memory = arm7_9_blank_check_memory,
+
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
.register_commands = arm720t_register_commands,
.target_command = arm720t_target_command,
.init_target = arm720t_init_target,
+ .examine = arm7tdmi_examine,
.quit = arm720t_quit
};
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_dr_scan(2, fields, -1);
if (clock)
jtag_add_runtest(0, -1);
jtag_execute_queue();
if (in)
- DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
+ LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
else
- DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+ LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
#else
- DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+ LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
#endif
return ERROR_OK;
/* examine cp15 control reg */
arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
jtag_execute_queue();
- DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
+ LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
/* save i/d fault status and address register */
- arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr);
- arm720t_read_cp15(target, 0xee160f10, &arm720t->far);
+ arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+ arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
jtag_execute_queue();
}
arm720t_common_t *arm720t = arm7tdmi->arch_info;
/* restore i/d fault status and address register */
- arm720t_write_cp15(target, 0xee050f10, arm720t->fsr);
- arm720t_write_cp15(target, 0xee060f10, arm720t->far);
+ arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
+ arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
}
int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
return ERROR_OK;
}
-int arm720t_arch_state(struct target_s *target, char *buf, int buf_size)
+int arm720t_arch_state(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
- ERROR("BUG: called for a non-ARMv4/5 target");
+ LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
- snprintf(buf, buf_size,
- "target halted in %s state due to %s, current mode: %s\n"
+ LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
- target_debug_reason_strings[target->debug_reason],
+ Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
arm720t_common_t *arm720t = arm7tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- if (target->state == TARGET_RUNNING)
+ target_halt(target);
+
+ long long then=timeval_ms();
+ int timeout;
+ while (!(timeout=((timeval_ms()-then)>1000)))
{
- target->type->halt(target);
+ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+ {
+ embeddedice_read_reg(dbg_stat);
+ jtag_execute_queue();
+ } else
+ {
+ break;
+ }
+ if (debug_level>=3)
+ {
+ alive_sleep(100);
+ } else
+ {
+ keep_alive();
+ }
}
-
- while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+ if (timeout)
{
- embeddedice_read_reg(dbg_stat);
- jtag_execute_queue();
+ LOG_ERROR("Failed to halt CPU after 1 sec");
+ return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;
}
-int arm720t_quit()
+int arm720t_quit(void)
{
return ERROR_OK;
int chain_pos;
char *variant = NULL;
arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t));
+ memset(arm720t, 0, sizeof(*arm720t));
if (argc < 4)
{
- ERROR("'target arm720t' requires at least one additional argument");
+ LOG_ERROR("'target arm720t' requires at least one additional argument");
exit(-1);
}
if (argc >= 5)
variant = args[4];
- DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
+ LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
arm720t_init_arch_info(target, arm720t, chain_pos, variant);
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