duan ellis target tcl work in progress
[fw/openocd] / src / target / arm720t.c
index 118fff45ea125fc9c7f182519268bdf7261412d4..fab553cfe6cfe5c72005333fcf54bae3fec635f1 100644 (file)
@@ -24,6 +24,7 @@
 #include "arm720t.h"
 #include "jtag.h"
 #include "log.h"
+#include "time_support.h"
 
 #include <stdlib.h>
 #include <string.h>
@@ -43,7 +44,7 @@ int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd,
 /* forward declarations */
 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int arm720t_quit();
+int arm720t_quit(void);
 int arm720t_arch_state(struct target_s *target);
 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
@@ -63,7 +64,6 @@ target_type_t arm720t_target =
        .assert_reset = arm7_9_assert_reset,
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm720t_soft_reset_halt,
-       .prepare_reset_halt = arm7_9_prepare_reset_halt,
        
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
@@ -71,6 +71,7 @@ target_type_t arm720t_target =
        .write_memory = arm720t_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
        .checksum_memory = arm7_9_checksum_memory,
+       .blank_check_memory = arm7_9_blank_check_memory,
        
        .run_algorithm = armv4_5_run_algorithm,
 
@@ -82,6 +83,7 @@ target_type_t arm720t_target =
        .register_commands = arm720t_register_commands,
        .target_command = arm720t_target_command,
        .init_target = arm720t_init_target,
+       .examine = arm7tdmi_examine,
        .quit = arm720t_quit
 };
 
@@ -319,7 +321,7 @@ int arm720t_arch_state(struct target_s *target)
                        "cpsr: 0x%8.8x pc: 0x%8.8x\n"
                        "MMU: %s, Cache: %s",
                         armv4_5_state_strings[armv4_5->core_state],
-                        target_debug_reason_strings[target->debug_reason],
+                        Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
                         armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
                         buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
                         buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
@@ -365,12 +367,13 @@ int arm720t_soft_reset_halt(struct target_s *target)
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
        arm720t_common_t *arm720t = arm7tdmi->arch_info;
-       int i;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
        
-       target->type->halt(target);
+       target_halt(target);
        
-       for (i=0; i<10; i++)
+       long long then=timeval_ms();
+       int timeout;
+       while (!(timeout=((timeval_ms()-then)>1000)))
        {
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
                {
@@ -380,10 +383,15 @@ int arm720t_soft_reset_halt(struct target_s *target)
                {
                        break;
                }
-               /* do not eat all CPU, time out after 1 se*/
-               usleep(100*1000);
+               if (debug_level>=3)
+               {
+                       alive_sleep(100);
+               } else
+               {
+                       keep_alive();
+               }
        }
-       if (i==10)
+       if (timeout)
        {
                LOG_ERROR("Failed to halt CPU after 1 sec");
                return ERROR_TARGET_TIMEOUT;
@@ -422,7 +430,7 @@ int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
        
 }
 
-int arm720t_quit()
+int arm720t_quit(void)
 {
        
        return ERROR_OK;