mips: fix gaffe when removing dynamic array allocation

[fw/openocd] / src / target / arm720t.c

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 4768f82d77da181fb292e9ff698e6c121ebf1793..f9388ab660eb3ff68b60ff257d582422067df4ee 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -225,7 +225,7 @@ static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 static int arm720t_arch_state(struct target *target)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
-       struct armv4_5_common_s *armv4_5;
+       struct arm *armv4_5;
 
        static const char *state[] =
        {
@@ -307,7 +307,7 @@ static int arm720t_soft_reset_halt(struct target *target)
        struct arm720t_common *arm720t = target_to_arm720(target);
        struct reg *dbg_stat = &arm720t->arm7_9_common
                        .eice_cache->reg_list[EICE_DBG_STAT];
-       struct armv4_5_common_s *armv4_5 = &arm720t->arm7_9_common
+       struct arm *armv4_5 = &arm720t->arm7_9_common
                        .armv4_5_common;
 
        if ((retval = target_halt(target)) != ERROR_OK)
@@ -347,18 +347,19 @@ static int arm720t_soft_reset_halt(struct target *target)
        target->state = TARGET_HALTED;
 
        /* SVC, ARM state, IRQ and FIQ disabled */
-       buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
+       uint32_t cpsr;
+
+       cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+       cpsr &= ~0xff;
+       cpsr |= 0xd3;
+       arm_set_cpsr(armv4_5, cpsr);
        armv4_5->cpsr->dirty = 1;
-       armv4_5->cpsr->valid = 1;
 
        /* start fetching from 0x0 */
        buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
        armv4_5->core_cache->reg_list[15].dirty = 1;
        armv4_5->core_cache->reg_list[15].valid = 1;
 
-       armv4_5->core_mode = ARMV4_5_MODE_SVC;
-       armv4_5->core_state = ARMV4_5_STATE_ARM;
-
        arm720t_disable_mmu_caches(target, 1, 1, 1);
        arm720t->armv4_5_mmu.mmu_enabled = 0;
        arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;