* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
- if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
- {
+ retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
return retval;
- }
- if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
- {
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
return retval;
- }
fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf;
fields[1].out_value = out_buf;
fields[1].in_value = NULL;
- if (in)
- {
+ if (in) {
fields[1].in_value = (uint8_t *)in;
jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
} else
- {
jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
- }
if (clock_arg)
jtag_add_runtest(0, TAP_DRPAUSE);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
return retval;
- }
if (in)
LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
static int arm720t_arch_state(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
- struct arm *armv4_5;
- static const char *state[] =
- {
+ static const char *state[] = {
"disabled", "enabled"
};
- armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
-
arm_arch_state(target);
LOG_USER("MMU: %s, Cache: %s",
state[arm720t->armv4_5_mmu.mmu_enabled],
struct arm720t_common *arm720t = target_to_arm720(target);
/* disable cache, but leave MMU enabled */
- if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
- {
+ if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
if (retval != ERROR_OK)
return retval;
}
retval = arm7_9_read_memory(target, address, size, count, buffer);
- if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
- {
+ if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
if (retval != ERROR_OK)
return retval;
}
static int arm720t_write_phys_memory(struct target *target,
- uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct arm720t_common *arm720t = target_to_arm720(target);
struct arm720t_common *arm720t = target_to_arm720(target);
struct reg *dbg_stat = &arm720t->arm7_9_common
.eice_cache->reg_list[EICE_DBG_STAT];
- struct arm *armv4_5 = &arm720t->arm7_9_common
- .armv4_5_common;
+ struct arm *arm = &arm720t->arm7_9_common.arm;
- if ((retval = target_halt(target)) != ERROR_OK)
- {
+ retval = target_halt(target);
+ if (retval != ERROR_OK)
return retval;
- }
long long then = timeval_ms();
int timeout;
- while (!(timeout = ((timeval_ms()-then) > 1000)))
- {
- if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
- {
+ while (!(timeout = ((timeval_ms()-then) > 1000))) {
+ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
embeddedice_read_reg(dbg_stat);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
return retval;
- }
} else
- {
break;
- }
if (debug_level >= 3)
- {
alive_sleep(100);
- } else
- {
+ else
keep_alive();
- }
}
- if (timeout)
- {
+ if (timeout) {
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
/* SVC, ARM state, IRQ and FIQ disabled */
uint32_t cpsr;
- cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+ cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
cpsr &= ~0xff;
cpsr |= 0xd3;
- arm_set_cpsr(armv4_5, cpsr);
- armv4_5->cpsr->dirty = 1;
+ arm_set_cpsr(arm, cpsr);
+ arm->cpsr->dirty = 1;
/* start fetching from 0x0 */
- buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
- armv4_5->pc->dirty = 1;
- armv4_5->pc->valid = 1;
+ buf_set_u32(arm->pc->value, 0, 32, 0x0);
+ arm->pc->dirty = 1;
+ arm->pc->valid = 1;
retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
if (retval != ERROR_OK)
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
- if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
- {
+ retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ if (retval != ERROR_OK)
return retval;
- }
return ERROR_OK;
}
{
struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
- arm7_9->armv4_5_common.mrc = arm720t_mrc;
- arm7_9->armv4_5_common.mcr = arm720t_mcr;
+ arm7_9->arm.mrc = arm720t_mrc;
+ arm7_9->arm.mcr = arm720t_mcr;
arm7tdmi_init_arch_info(target, arm7_9, tap);
{
struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
- arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
+ arm720t->arm7_9_common.arm.is_armv4 = true;
return arm720t_init_arch_info(target, arm720t, target->tap);
}
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm720t_common *arm720t = target_to_arm720(target);
- struct arm_jtag *jtag_info;
retval = arm720t_verify_pointer(CMD_CTX, arm720t);
if (retval != ERROR_OK)
return retval;
- jtag_info = &arm720t->arm7_9_common.jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
/* one or more argument, access a single register (write if second argument is given */
- if (CMD_ARGC >= 1)
- {
+ if (CMD_ARGC >= 1) {
uint32_t opcode;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
- if (CMD_ARGC == 1)
- {
+ if (CMD_ARGC == 1) {
uint32_t value;
- if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
- {
+ retval = arm720t_read_cp15(target, opcode, &value);
+ if (retval != ERROR_OK) {
command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
return ERROR_OK;
}
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
return retval;
- }
command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
- }
- else if (CMD_ARGC == 2)
- {
+ } else if (CMD_ARGC == 2) {
uint32_t value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
- if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
- {
+ retval = arm720t_write_cp15(target, opcode, value);
+ if (retval != ERROR_OK) {
command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
return ERROR_OK;
}
uint32_t CRn, uint32_t CRm,
uint32_t *value)
{
- if (cpnum!=15)
- {
+ if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
uint32_t CRn, uint32_t CRm,
uint32_t value)
{
- if (cpnum!=15)
- {
+ if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
.name = "arm720t",
.mode = COMMAND_ANY,
.help = "arm720t command group",
+ .usage = "",
.chain = arm720t_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
/** Holds methods for ARM720 targets. */
-struct target_type arm720t_target =
-{
+struct target_type arm720t_target = {
.name = "arm720t",
.poll = arm7_9_poll,
projects / fw / openocd / blobdiff