#endif
static int arm720t_scan_cp15(struct target *target,
- uint32_t out, uint32_t *in, int instruction, int clock)
+ uint32_t out, uint32_t *in, int instruction, int clock_arg)
{
int retval;
struct arm720t_common *arm720t = target_to_arm720(target);
jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
}
- if (clock)
+ if (clock_arg)
jtag_add_runtest(0, TAP_DRPAUSE);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
if (in)
LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
else
- LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+ LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
#else
- LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
+ LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
#endif
return ERROR_OK;
return ERROR_OK;
}
-static uint32_t arm720t_get_ttb(struct target *target)
+static int arm720t_get_ttb(struct target *target, uint32_t *result)
{
uint32_t ttb = 0x0;
- arm720t_read_cp15(target, 0xee120f10, &ttb);
- jtag_execute_queue();
+ int retval;
+
+ retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
ttb &= 0xffffc000;
- return ttb;
+ *result = ttb;
+
+ return ERROR_OK;
}
-static void arm720t_disable_mmu_caches(struct target *target,
+static int arm720t_disable_mmu_caches(struct target *target,
int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- arm720t_read_cp15(target, 0xee110f10, &cp15_control);
- jtag_execute_queue();
+ retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
cp15_control &= ~0x1U;
if (d_u_cache || i_cache)
cp15_control &= ~0x4U;
- arm720t_write_cp15(target, 0xee010f10, cp15_control);
+ retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+ return retval;
}
-static void arm720t_enable_mmu_caches(struct target *target,
+static int arm720t_enable_mmu_caches(struct target *target,
int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- arm720t_read_cp15(target, 0xee110f10, &cp15_control);
- jtag_execute_queue();
+ retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
cp15_control |= 0x1U;
if (d_u_cache || i_cache)
cp15_control |= 0x4U;
- arm720t_write_cp15(target, 0xee010f10, cp15_control);
+ retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+ return retval;
}
-static void arm720t_post_debug_entry(struct target *target)
+static int arm720t_post_debug_entry(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
+ int retval;
/* examine cp15 control reg */
- arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
- jtag_execute_queue();
+ retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
/* save i/d fault status and address register */
- arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
- arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
- jtag_execute_queue();
+ retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ return retval;
}
static void arm720t_pre_restore_context(struct target *target)
static int arm720_virt2phys(struct target *target,
uint32_t virtual, uint32_t *physical)
{
- int type;
uint32_t cb;
- int domain;
- uint32_t ap;
struct arm720t_common *arm720t = target_to_arm720(target);
- uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
- if (type == -1)
- {
- return ret;
- }
+ uint32_t ret;
+ int retval = armv4_5_mmu_translate_va(target,
+ &arm720t->armv4_5_mmu, virtual, &cb, &ret);
+ if (retval != ERROR_OK)
+ return retval;
*physical = ret;
return ERROR_OK;
}
/* disable cache, but leave MMU enabled */
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
- arm720t_disable_mmu_caches(target, 0, 1, 0);
-
+ {
+ retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
+ if (retval != ERROR_OK)
+ return retval;
+ }
retval = arm7_9_read_memory(target, address, size, count, buffer);
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
- arm720t_enable_mmu_caches(target, 0, 1, 0);
+ {
+ retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
+ if (retval != ERROR_OK)
+ return retval;
+ }
return retval;
}
armv4_5->pc->dirty = 1;
armv4_5->pc->valid = 1;
- arm720t_disable_mmu_caches(target, 1, 1, 1);
+ retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
+ if (retval != ERROR_OK)
+ return retval;
arm720t->armv4_5_mmu.mmu_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;