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stlink: add missing memory check handlers
[fw/openocd] / src / target / arm720t.c
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index b269f9488eda5acd43ed8bb652df6eea3f6f1024..94af0f7f814a47b7f99fc11672a9dfa7bed9365d 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -154,14 +154,19 @@ static int arm720t_get_ttb(struct target *target, uint32_t *result)
        return ERROR_OK;
 }
 
-static void arm720t_disable_mmu_caches(struct target *target,
+static int arm720t_disable_mmu_caches(struct target *target,
                int mmu, int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control &= ~0x1U;
@@ -169,17 +174,23 @@ static void arm720t_disable_mmu_caches(struct target *target,
        if (d_u_cache || i_cache)
                cp15_control &= ~0x4U;
 
-       arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       return retval;
 }
 
-static void arm720t_enable_mmu_caches(struct target *target,
+static int arm720t_enable_mmu_caches(struct target *target,
                int mmu, int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -187,16 +198,22 @@ static void arm720t_enable_mmu_caches(struct target *target,
        if (d_u_cache || i_cache)
                cp15_control |= 0x4U;
 
-       arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       return retval;
 }
 
-static void arm720t_post_debug_entry(struct target *target)
+static int arm720t_post_debug_entry(struct target *target)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
        arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
@@ -204,9 +221,14 @@ static void arm720t_post_debug_entry(struct target *target)
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
        /* save i/d fault status and address register */
-       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
-       arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       return retval;
 }
 
 static void arm720t_pre_restore_context(struct target *target)
@@ -231,15 +253,12 @@ static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 static int arm720t_arch_state(struct target *target)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
-       struct arm *armv4_5;
 
        static const char *state[] =
        {
                "disabled", "enabled"
        };
 
-       armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, Cache: %s",
                         state[arm720t->armv4_5_mmu.mmu_enabled],
@@ -282,12 +301,19 @@ static int arm720t_read_memory(struct target *target,
 
        /* disable cache, but leave MMU enabled */
        if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-               arm720t_disable_mmu_caches(target, 0, 1, 0);
-
+       {
+               retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
        retval = arm7_9_read_memory(target, address, size, count, buffer);
 
        if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-               arm720t_enable_mmu_caches(target, 0, 1, 0);
+       {
+               retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
 
        return retval;
 }
@@ -301,7 +327,7 @@ static int arm720t_read_phys_memory(struct target *target,
 }
 
 static int arm720t_write_phys_memory(struct target *target,
-               uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
 
@@ -314,8 +340,7 @@ static int arm720t_soft_reset_halt(struct target *target)
        struct arm720t_common *arm720t = target_to_arm720(target);
        struct reg *dbg_stat = &arm720t->arm7_9_common
                        .eice_cache->reg_list[EICE_DBG_STAT];
-       struct arm *armv4_5 = &arm720t->arm7_9_common
-                       .armv4_5_common;
+       struct arm *arm = &arm720t->arm7_9_common.arm;
 
        if ((retval = target_halt(target)) != ERROR_OK)
        {
@@ -356,18 +381,20 @@ static int arm720t_soft_reset_halt(struct target *target)
        /* SVC, ARM state, IRQ and FIQ disabled */
        uint32_t cpsr;
 
-       cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+       cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
        cpsr &= ~0xff;
        cpsr |= 0xd3;
-       arm_set_cpsr(armv4_5, cpsr);
-       armv4_5->cpsr->dirty = 1;
+       arm_set_cpsr(arm, cpsr);
+       arm->cpsr->dirty = 1;
 
        /* start fetching from 0x0 */
-       buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
-       armv4_5->pc->dirty = 1;
-       armv4_5->pc->valid = 1;
+       buf_set_u32(arm->pc->value, 0, 32, 0x0);
+       arm->pc->dirty = 1;
+       arm->pc->valid = 1;
 
-       arm720t_disable_mmu_caches(target, 1, 1, 1);
+       retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
+       if (retval != ERROR_OK)
+               return retval;
        arm720t->armv4_5_mmu.mmu_enabled = 0;
        arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
@@ -400,8 +427,8 @@ static int arm720t_init_arch_info(struct target *target,
 {
        struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 
-       arm7_9->armv4_5_common.mrc = arm720t_mrc;
-       arm7_9->armv4_5_common.mcr = arm720t_mcr;
+       arm7_9->arm.mrc = arm720t_mrc;
+       arm7_9->arm.mcr = arm720t_mcr;
 
        arm7tdmi_init_arch_info(target, arm7_9, tap);
 
@@ -426,7 +453,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 {
        struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 
-       arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
+       arm720t->arm7_9_common.arm.is_armv4 = true;
        return arm720t_init_arch_info(target, arm720t, target->tap);
 }
 
@@ -435,13 +462,11 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
        int retval;
        struct target *target = get_current_target(CMD_CTX);
        struct arm720t_common *arm720t = target_to_arm720(target);
-       struct arm_jtag *jtag_info;
 
        retval = arm720t_verify_pointer(CMD_CTX, arm720t);
        if (retval != ERROR_OK)
                return retval;
 
-       jtag_info = &arm720t->arm7_9_common.jtag_info;
 
        if (target->state != TARGET_HALTED)
        {
@@ -544,6 +569,7 @@ static const struct command_registration arm720t_command_handlers[] = {
                .name = "arm720t",
                .mode = COMMAND_ANY,
                .help = "arm720t command group",
+               .usage = "",
                .chain = arm720t_exec_command_handlers,
        },
        COMMAND_REGISTRATION_DONE
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