#include "config.h"
#endif
-#include "arm11.h"
+#include "arm_jtag.h"
+#include "arm11_dbgtap.h"
#include "time_support.h"
Conversely there may be other places in this code where the ARM11 code relies
on the driver to hit through RTI when coming from Update-?R.
*/
-tap_state_t arm11_move_pi_to_si_via_ci[] =
+static const tap_state_t arm11_move_pi_to_si_via_ci[] =
{
TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
};
-int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
+int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state)
{
if (cmd_queue_cur_state == TAP_IRPAUSE)
- jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
+ jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
jtag_add_ir_scan(num_fields, fields, state);
return ERROR_OK;
}
-tap_state_t arm11_move_pd_to_sd_via_cd[] =
+static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
-int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
+int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state)
{
if (cmd_queue_cur_state == TAP_DRPAUSE)
- jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
+ jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
jtag_add_dr_scan(num_fields, fields, state);
return ERROR_OK;
}
-/** Code de-clutter: Construct scan_field_t to write out a value
+/** Code de-clutter: Construct struct scan_field to write out a value
*
* \param arm11 Target state variable.
* \param num_bits Length of the data field
* <em > (data is written when the JTAG queue is executed)</em>
* \param field target data structure that will be initialized
*/
-void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
+void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field)
{
field->tap = arm11->target->tap;
field->num_bits = num_bits;
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state)
+void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
{
- jtag_tap_t *tap;
+ struct jtag_tap *tap;
tap = arm11->target->tap;
if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
JTAG_DEBUG("IR <= 0x%02x", instr);
- scan_field_t field;
+ struct scan_field field;
arm11_setup_field(arm11, 5, &instr, NULL, &field);
}
/** Verify shifted out data from Scan Chain Register (SCREG)
- * Used as parameter to scan_field_t::in_handler in
+ * Used as parameter to struct scan_field::in_handler in
* arm11_add_debug_SCAN_N().
*
*/
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-int arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
+int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state_t state)
{
JTAG_DEBUG("SCREG <= 0x%02x", chain);
arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
- scan_field_t field;
+ struct scan_field field;
uint8_t tmp[1];
arm11_setup_field(arm11, 5, &chain, &tmp, &field);
arm11_in_handler_SCAN_N(tmp);
+ arm11->jtag_info.cur_scan_chain = chain;
+
return jtag_execute_queue();
}
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
+void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", inst);
- scan_field_t itr[2];
+ struct scan_field itr[2];
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
- arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
}
/** Read the Debug Status and Control Register (DSCR)
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
+int arm11_read_DSCR(struct arm11_common * arm11, uint32_t *value)
{
int retval;
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
uint32_t dscr;
- scan_field_t chain1_field;
+ struct scan_field chain1_field;
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr)
+int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
{
int retval;
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
- scan_field_t chain1_field;
+ struct scan_field chain1_field;
arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
* \param arm11 Target state variable.
*
*/
-int arm11_run_instr_data_prepare(arm11_common_t * arm11)
+int arm11_run_instr_data_prepare(struct arm11_common * arm11)
{
return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
}
* \param arm11 Target state variable.
*
*/
-int arm11_run_instr_data_finish(arm11_common_t * arm11)
+int arm11_run_instr_data_finish(struct arm11_common * arm11)
{
return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
}
* \param count Number of opcodes to execute
*
*/
-int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t count)
+int arm11_run_instr_no_data(struct arm11_common * arm11, uint32_t * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
* \param opcode ARM opcode
*
*/
-int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
+int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode)
{
return arm11_run_instr_no_data(arm11, &opcode, 1);
}
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
- scan_field_t chain5_fields[3];
+ struct scan_field chain5_fields[3];
uint32_t Data;
uint8_t Ready;
{
Data = *data;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
CHECK_RETVAL(jtag_execute_queue());
{
Data = 0;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
* https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
* https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
*/
-tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
+static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
- scan_field_t chain5_fields[3];
+ struct scan_field chain5_fields[3];
arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
Readies = (uint8_t *) malloc(bytes);
if (Readies == NULL)
{
- LOG_ERROR("Out of memory allocating %d bytes", bytes);
+ LOG_ERROR("Out of memory allocating " ZU " bytes", bytes);
return ERROR_FAIL;
}
if (count)
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE));
- jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
+ jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE));
+ jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
}
else
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
}
}
chain5_fields[0].out_value = 0;
chain5_fields[1].in_value = ReadyPos++;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
int retval = jtag_execute_queue();
if (retval == ERROR_OK)
* \param data Data word to be passed to the core via DTR
*
*/
-int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
+int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
{
return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
* \param count Number of data words and instruction repetitions
*
*/
-int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
- scan_field_t chain5_fields[3];
+ struct scan_field chain5_fields[3];
uint32_t Data;
uint8_t Ready;
int i = 0;
do
{
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
* \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
*
*/
-int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
+int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data)
{
int retval;
retval = arm11_run_instr_no_data1(arm11, opcode);
* \param data Data word that will be written to r0 before \p opcode is executed
*
*/
-int arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
+int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
{
int retval;
/* MRC p14,0,r0,c0,c5,0 */
/** Apply reads and writes to scan chain 7
*
- * \see arm11_sc7_action_t
+ * \see struct arm11_sc7_action
*
* \param arm11 Target state variable.
* \param actions A list of read and/or write instructions
* \param count Number of instructions in the list.
*
*/
-int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
+int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions, size_t count)
{
int retval;
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
- scan_field_t chain7_fields[3];
+ struct scan_field chain7_fields[3];
uint8_t nRW;
uint32_t DataOut;
{
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
- arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields), chain7_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
* \param arm11 Target state variable.
*
*/
-void arm11_sc7_clear_vbw(arm11_common_t * arm11)
+void arm11_sc7_clear_vbw(struct arm11_common * arm11)
{
- arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
- arm11_sc7_action_t * pos = clear_bw;
+ struct arm11_sc7_action clear_bw[arm11->brp + arm11->wrp + 1];
+ struct arm11_sc7_action * pos = clear_bw;
- for (size_t i = 0; i < asizeof(clear_bw); i++)
+ for (size_t i = 0; i < ARRAY_SIZE(clear_bw); i++)
{
clear_bw[i].write = true;
clear_bw[i].value = 0;
(pos++)->address = ARM11_SC7_VCR;
- arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
+ arm11_sc7_run(arm11, clear_bw, ARRAY_SIZE(clear_bw));
}
/** Write VCR register
* \param arm11 Target state variable.
* \param value Value to be written
*/
-void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value)
+void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
{
- arm11_sc7_action_t set_vcr;
+ struct arm11_sc7_action set_vcr;
set_vcr.write = true;
set_vcr.address = ARM11_SC7_VCR;
* \param result Pointer where to store result
*
*/
-int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result)
+int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result)
{
- arm11_run_instr_data_prepare(arm11);
+ int retval;
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
- arm11_run_instr_data_finish(arm11);
-
- return ERROR_OK;
+ return arm11_run_instr_data_finish(arm11);
}
-