#include "arm_jtag.h"
#include "arm11_dbgtap.h"
-#include "time_support.h"
+#include <helper/time_support.h>
#if 0
-#define JTAG_DEBUG(expr ...) DEBUG(expr)
+#define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0)
#else
-#define JTAG_DEBUG(expr ...) do {} while (0)
+#define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0)
#endif
/*
};
-static int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields,
+/* REVISIT no error handling here! */
+static void arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields,
tap_state_t state)
{
if (cmd_queue_cur_state == TAP_IRPAUSE)
jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
jtag_add_ir_scan(num_fields, fields, state);
- return ERROR_OK;
}
static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
-int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state)
+/* REVISIT no error handling here! */
+void arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields,
+ tap_state_t state)
{
if (cmd_queue_cur_state == TAP_DRPAUSE)
jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
jtag_add_dr_scan(num_fields, fields, state);
- return ERROR_OK;
}
* <em > (data is written when the JTAG queue is executed)</em>
* \param field target data structure that will be initialized
*/
-void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field)
+void arm11_setup_field(struct arm11_common *arm11, int num_bits,
+ void *out_data, void *in_data, struct scan_field *field)
{
- field->tap = arm11->target->tap;
+ field->tap = arm11->arm.target->tap;
field->num_bits = num_bits;
field->out_value = out_data;
field->in_value = in_data;
}
+static const char *arm11_ir_to_string(uint8_t ir)
+{
+ const char *s = "unknown";
+
+ switch (ir) {
+ case ARM11_EXTEST:
+ s = "EXTEST";
+ break;
+ case ARM11_SCAN_N:
+ s = "SCAN_N";
+ break;
+ case ARM11_RESTART:
+ s = "RESTART";
+ break;
+ case ARM11_HALT:
+ s = "HALT";
+ break;
+ case ARM11_INTEST:
+ s = "INTEST";
+ break;
+ case ARM11_ITRSEL:
+ s = "ITRSEL";
+ break;
+ case ARM11_IDCODE:
+ s = "IDCODE";
+ break;
+ case ARM11_BYPASS:
+ s = "BYPASS";
+ break;
+ }
+ return s;
+}
/** Write JTAG instruction register
*
*/
void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
{
- struct jtag_tap *tap;
- tap = arm11->target->tap;
+ struct jtag_tap *tap = arm11->arm.target->tap;
if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
{
return;
}
- JTAG_DEBUG("IR <= 0x%02x", instr);
+ JTAG_DEBUG("IR <= %s (0x%02x)", arm11_ir_to_string(instr), instr);
struct scan_field field;
arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
}
-/** Verify shifted out data from Scan Chain Register (SCREG)
- * Used as parameter to struct scan_field::in_handler in
- * arm11_add_debug_SCAN_N().
- *
- */
+/** Verify data shifted out from Scan Chain Register (SCREG). */
static void arm11_in_handler_SCAN_N(uint8_t *in_value)
{
- /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */
+ /* Don't expect JTAG layer to modify bits we didn't ask it to read */
uint8_t v = *in_value & 0x1F;
if (v != 0x10)
{
- LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
+ LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v);
jtag_set_error(ERROR_FAIL);
}
-
- JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
}
/** Select and write to Scan Chain Register (SCREG)
* \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
* value (Pause-DR).
*
+ * Changes the current scan chain if needed, transitions to the specified
+ * TAP state, and leaves the IR undefined.
+ *
* The chain takes effect when Update-DR is passed (usually when subsequently
* the INTEXT/EXTEST instructions are written).
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state_t state)
+int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
+ uint8_t chain, tap_state_t state)
{
- JTAG_DEBUG("SCREG <= 0x%02x", chain);
+ /* Don't needlessly switch the scan chain.
+ * NOTE: the ITRSEL instruction fakes SCREG changing;
+ * but leaves its actual value unchanged.
+ */
+ if (arm11->jtag_info.cur_scan_chain == chain) {
+ JTAG_DEBUG("SCREG <= %d SKIPPED", chain);
+ return jtag_add_statemove((state == ARM11_TAP_DEFAULT)
+ ? TAP_DRPAUSE : state);
+ }
+ JTAG_DEBUG("SCREG <= %d", chain);
arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
return jtag_execute_queue();
}
-/** Write an instruction into the ITR register
+/**
+ * Queue a DR scan of the ITR register. Caller must have selected
+ * scan chain 4 (ITR), possibly using ITRSEL.
*
* \param arm11 Target state variable.
* \param inst An ARM11 processor instruction/opcode.
- * \param flag Optional parameter to retrieve the InstCompl flag
- * (this will be written when the JTAG chain is executed).
- * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
- * value (Run-Test/Idle).
+ * \param flag Optional parameter to retrieve the Ready flag;
+ * this address will be written when the JTAG chain is scanned.
+ * \param state The TAP state to enter after the DR scan.
*
- * \remarks By default this ends with Run-Test/Idle state
- * and causes the instruction to be executed. If
- * a subsequent write to DTR is needed before
- * executing the instruction then TAP_DRPAUSE should be
- * passed to \p state.
+ * Going through the TAP_DRUPDATE state writes ITR only if Ready was
+ * previously set. Only the Ready flag is readable by the scan.
*
- * \remarks This adds to the JTAG command queue but does \em not execute it.
+ * An instruction loaded into ITR is executed when going through the
+ * TAP_IDLE state only if Ready was previously set and the debug state
+ * is properly set up. Depending on the instruction, you may also need
+ * to ensure that the rDTR is ready before that Run-Test/Idle state.
*/
static void arm11_add_debug_INST(struct arm11_common * arm11,
uint32_t inst, uint8_t * flag, tap_state_t state)
{
- JTAG_DEBUG("INST <= 0x%08x", inst);
+ JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
struct scan_field itr[2];
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
- arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state);
}
-/** Read the Debug Status and Control Register (DSCR)
- *
- * same as CP14 c1
+/**
+ * Read and save the Debug Status and Control Register (DSCR).
*
* \param arm11 Target state variable.
- * \param value DSCR content
- * \return Error status
+ * \return Error status; arm11->dscr is updated on success.
*
- * \remarks This is a stand-alone function that executes the JTAG command queue.
+ * \remarks This is a stand-alone function that executes the JTAG
+ * command queue. It does not require the ARM11 debug TAP to be
+ * in any particular state.
*/
-int arm11_read_DSCR(struct arm11_common * arm11, uint32_t *value)
+int arm11_read_DSCR(struct arm11_common *arm11)
{
int retval;
+
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
if (retval != ERROR_OK)
return retval;
CHECK_RETVAL(jtag_execute_queue());
- if (arm11->last_dscr != dscr)
- JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
-
- arm11->last_dscr = dscr;
+ if (arm11->dscr != dscr)
+ JTAG_DEBUG("DSCR = %08x (OLD %08x)",
+ (unsigned) dscr,
+ (unsigned) arm11->dscr);
- *value = dscr;
+ arm11->dscr = dscr;
return ERROR_OK;
}
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
+ JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
+ (unsigned) dscr,
+ (unsigned) arm11->dscr);
- arm11->last_dscr = dscr;
+ arm11->dscr = dscr;
return ERROR_OK;
}
-
-
-/** Get the debug reason from Debug Status and Control Register (DSCR)
- *
- * \param dscr DSCR value to analyze
- * \return Debug reason
- *
- */
-enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
-{
- switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
- {
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
- LOG_INFO("Debug entry: JTAG HALT");
- return DBG_REASON_DBGRQ;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
- LOG_INFO("Debug entry: breakpoint");
- return DBG_REASON_BREAKPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
- LOG_INFO("Debug entry: watchpoint");
- return DBG_REASON_WATCHPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
- LOG_INFO("Debug entry: BKPT instruction");
- return DBG_REASON_BREAKPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
- LOG_INFO("Debug entry: EDBGRQ signal");
- return DBG_REASON_DBGRQ;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
- LOG_INFO("Debug entry: VCR vector catch");
- return DBG_REASON_BREAKPOINT;
-
- default:
- LOG_INFO("Debug entry: unknown");
- return DBG_REASON_DBGRQ;
- }
-};
-
-
-
/** Prepare the stage for ITR/DTR operations
* from the arm11_run_instr... group of functions.
*
-/** Execute one or multiple instructions via ITR
+/**
+ * Execute one or more instructions via ITR.
+ * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
+ * is set, the ITR Ready flag is set (as seen on the previous entry to
+ * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
*
/** Execute one instruction via ITR repeatedly while
* passing data to the core via DTR on each execution.
*
+ * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
+ * is set, the ITR Ready flag is set (as seen on the previous entry to
+ * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
+ *
* The executed instruction \em must read data from DTR.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+ JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
+ (unsigned) Data, Ready, nRetry);
long long then = 0;
/** Execute one instruction via ITR repeatedly while
* passing data to the core via DTR on each execution.
*
+ * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
+ * is set, the ITR Ready flag is set (as seen on the previous entry to
+ * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
+ *
* No Ready check during transmission.
*
* The executed instruction \em must read data from DTR.
/** Execute one instruction via ITR repeatedly while
* reading data from the core via DTR on each execution.
*
+ * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
+ * is set, the ITR Ready flag is set (as seen on the previous entry to
+ * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
+ *
* The executed instruction \em must write data to DTR.
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+ JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
+ (unsigned) Data, Ready, nRetry);
long long then = 0;
}
else
{
- nRW = 0;
+ nRW = 1;
DataOut = 0;
AddressOut = 0;
}
do
{
- JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
+ JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
+ (unsigned) AddressOut,
+ (unsigned) DataOut,
+ nRW ? "write" : "read");
- arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields), chain7_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields),
+ chain7_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
+ if (!Ready)
+ JTAG_DEBUG("SC7 => !ready");
}
while (!Ready); /* 'nRW' is 'Ready' on read out */
+ if (!nRW)
+ JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn);
+
if (i > 0)
{
if (actions[i - 1].address != AddressIn)
}
}
}
-
- for (size_t i = 0; i < count; i++)
- {
- JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
- }
-
return ERROR_OK;
}
*/
void arm11_sc7_clear_vbw(struct arm11_common * arm11)
{
- size_t clear_bw_size = arm11->brp + arm11->wrp + 1;
+ size_t clear_bw_size = arm11->brp + 1;
struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
struct arm11_sc7_action * pos = clear_bw;
for (size_t i = 0; i < arm11->brp; i++)
(pos++)->address = ARM11_SC7_BCR0 + i;
-
- for (size_t i = 0; i < arm11->wrp; i++)
- (pos++)->address = ARM11_SC7_WCR0 + i;
-
-
(pos++)->address = ARM11_SC7_VCR;
arm11_sc7_run(arm11, clear_bw, clear_bw_size);
set_vcr.address = ARM11_SC7_VCR;
set_vcr.value = value;
-
arm11_sc7_run(arm11, &set_vcr, 1);
}
opcode, data);
}
+/* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint
+ * and watchpoint operations instead of running them right away. Since we
+ * pre-allocated our vector, we don't need to worry about space.
+ */
+static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+ uint32_t addr, uint32_t control)
+{
+ struct arm11_common *arm11 = dpm_to_arm11(dpm);
+ struct arm11_sc7_action *action;
+
+ action = arm11->bpwp_actions + arm11->bpwp_n;
+
+ /* Invariant: this bp/wp is disabled.
+ * It also happens that the core is halted here, but for
+ * DPM-based cores we don't actually care about that.
+ */
+
+ action[0].write = action[1].write = true;
+
+ action[0].value = addr;
+ action[1].value = control;
+
+ switch (index) {
+ case 0 ... 15:
+ action[0].address = ARM11_SC7_BVR0 + index;
+ action[1].address = ARM11_SC7_BCR0 + index;
+ break;
+ case 16 ... 32:
+ index -= 16;
+ action[0].address = ARM11_SC7_WVR0 + index;
+ action[1].address = ARM11_SC7_WCR0 + index;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+
+ arm11->bpwp_n += 2;
-void arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
+ return ERROR_OK;
+}
+
+static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+{
+ struct arm11_common *arm11 = dpm_to_arm11(dpm);
+ struct arm11_sc7_action *action;
+
+ action = arm11->bpwp_actions + arm11->bpwp_n;
+
+ action[0].write = true;
+ action[0].value = 0;
+
+ switch (index) {
+ case 0 ... 15:
+ action[0].address = ARM11_SC7_BCR0 + index;
+ break;
+ case 16 ... 32:
+ index -= 16;
+ action[0].address = ARM11_SC7_WCR0 + index;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+
+ arm11->bpwp_n += 1;
+
+ return ERROR_OK;
+}
+
+/** Flush any pending breakpoint and watchpoint updates. */
+int arm11_bpwp_flush(struct arm11_common *arm11)
+{
+ int retval;
+
+ if (!arm11->bpwp_n)
+ return ERROR_OK;
+
+ retval = arm11_sc7_run(arm11, arm11->bpwp_actions, arm11->bpwp_n);
+ arm11->bpwp_n = 0;
+
+ return retval;
+}
+
+/** Set up high-level debug module utilities */
+int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
{
struct arm_dpm *dpm = &arm11->dpm;
+ int retval;
dpm->arm = &arm11->arm;
dpm->instr_read_data_dcc = arm11_dpm_instr_read_data_dcc;
dpm->instr_read_data_r0 = arm11_dpm_instr_read_data_r0;
+
+ dpm->bpwp_enable = arm11_bpwp_enable;
+ dpm->bpwp_disable = arm11_bpwp_disable;
+
+ retval = arm_dpm_setup(dpm);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* alloc enough to enable all breakpoints and watchpoints at once */
+ arm11->bpwp_actions = calloc(2 * (dpm->nbp + dpm->nwp),
+ sizeof *arm11->bpwp_actions);
+ if (!arm11->bpwp_actions)
+ return ERROR_FAIL;
+
+ retval = arm_dpm_initialize(dpm);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return arm11_bpwp_flush(arm11);
}
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