-/***************************************************************************\r
- * Copyright (C) 2008 digenius technology GmbH. *\r
- * *\r
- * This program is free software; you can redistribute it and/or modify *\r
- * it under the terms of the GNU General Public License as published by *\r
- * the Free Software Foundation; either version 2 of the License, or *\r
- * (at your option) any later version. *\r
- * *\r
- * This program is distributed in the hope that it will be useful, *\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
- * GNU General Public License for more details. *\r
- * *\r
- * You should have received a copy of the GNU General Public License *\r
- * along with this program; if not, write to the *\r
- * Free Software Foundation, Inc., *\r
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
- ***************************************************************************/\r
-\r
-#ifndef ARM11_H\r
-#define ARM11_H\r
-\r
-#include "target.h"\r
-#include "register.h"\r
-#include "embeddedice.h"\r
-#include "arm_jtag.h"\r
-\r
-\r
-#define bool int\r
-#define true 1\r
-#define false 0\r
-\r
-#define asizeof(x) (sizeof(x) / sizeof((x)[0]))\r
-\r
-#define NEW(type, variable, items) \\r
- type * variable = malloc(sizeof(type) * items)\r
-\r
-\r
-#define ARM11_REGCACHE_MODEREGS 0\r
-#define ARM11_REGCACHE_FREGS 0\r
-\r
-#define ARM11_REGCACHE_COUNT (20 + \\r
- 23 * ARM11_REGCACHE_MODEREGS + \\r
- 9 * ARM11_REGCACHE_FREGS)\r
-\r
-\r
-typedef struct arm11_register_history_s\r
-{\r
- u32 value;\r
- u8 valid;\r
-}arm11_register_history_t;\r
-\r
-\r
-\r
-typedef struct arm11_common_s\r
-{\r
- target_t * target;\r
-\r
- arm_jtag_t jtag_info;\r
-\r
- /** \name Processor type detection */\r
- /*@{*/\r
-\r
- u32 device_id; /**< IDCODE readout */\r
- u32 didr; /**< DIDR readout (debug capabilities) */\r
- u8 implementor; /**< DIDR Implementor readout */\r
-\r
- size_t brp; /**< Number of Breakpoint Register Pairs */\r
- size_t wrp; /**< Number of Watchpoint Register Pairs */\r
-\r
- /*@}*/\r
-\r
-\r
- u32 last_dscr; /**< Last retrieved DSCR value;\r
- * Can be used to detect changes */\r
-\r
- u8 trst_active;\r
- u8 halt_requested;\r
-\r
- /** \name Shadow registers to save processor state */\r
- /*@{*/\r
-\r
- reg_t * reg_list; /**< target register list */\r
- u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */\r
-\r
- /*@}*/\r
-\r
- arm11_register_history_t\r
- reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */\r
-\r
-\r
-} arm11_common_t;\r
-\r
-\r
-/**\r
- * ARM11 DBGTAP instructions \r
- * \r
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html\r
- */\r
-enum arm11_instructions\r
-{\r
- ARM11_EXTEST = 0x00,\r
- ARM11_SCAN_N = 0x02,\r
- ARM11_RESTART = 0x04,\r
- ARM11_HALT = 0x08,\r
- ARM11_INTEST = 0x0C,\r
- ARM11_ITRSEL = 0x1D,\r
- ARM11_IDCODE = 0x1E,\r
- ARM11_BYPASS = 0x1F,\r
-};\r
-\r
-enum arm11_dscr\r
-{\r
- ARM11_DSCR_CORE_HALTED = 1 << 0,\r
- ARM11_DSCR_CORE_RESTARTED = 1 << 1,\r
-\r
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,\r
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,\r
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,\r
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,\r
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,\r
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,\r
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,\r
-\r
- ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,\r
- ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,\r
- ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,\r
- ARM11_DSCR_MODE_SELECT = 1 << 14,\r
- ARM11_DSCR_WDTR_FULL = 1 << 29,\r
- ARM11_DSCR_RDTR_FULL = 1 << 30,\r
-};\r
-\r
-enum arm11_cpsr\r
-{\r
- ARM11_CPSR_T = 1 << 5,\r
- ARM11_CPSR_J = 1 << 24,\r
-};\r
-\r
-enum arm11_sc7\r
-{\r
- ARM11_SC7_NULL = 0,\r
- ARM11_SC7_VCR = 7,\r
- ARM11_SC7_PC = 8,\r
- ARM11_SC7_BVR0 = 64,\r
- ARM11_SC7_BCR0 = 80,\r
- ARM11_SC7_WVR0 = 96,\r
- ARM11_SC7_WCR0 = 112,\r
-};\r
-\r
-\r
-\r
-typedef struct arm11_reg_state_s\r
-{\r
- u32 def_index;\r
- target_t * target;\r
-} arm11_reg_state_t;\r
-\r
-\r
-\r
-\r
-/* poll current target status */\r
-int arm11_poll(struct target_s *target);\r
-/* architecture specific status reply */\r
-int arm11_arch_state(struct target_s *target);\r
-\r
-/* target request support */\r
-int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);\r
-\r
-/* target execution control */\r
-int arm11_halt(struct target_s *target);\r
-int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);\r
-int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);\r
-\r
-/* target reset control */\r
-int arm11_assert_reset(struct target_s *target);\r
-int arm11_deassert_reset(struct target_s *target);\r
-int arm11_soft_reset_halt(struct target_s *target);\r
-int arm11_prepare_reset_halt(struct target_s *target);\r
-\r
-/* target register access for gdb */\r
-int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);\r
-\r
-/* target memory access \r
-* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)\r
-* count: number of items of <size>\r
-*/\r
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
-\r
-/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */\r
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);\r
-\r
-int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);\r
-\r
-/* target break-/watchpoint control \r
-* rw: 0 = write, 1 = read, 2 = access\r
-*/\r
-int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);\r
-int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);\r
-int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);\r
-int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);\r
-\r
-/* target algorithm support */\r
-int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);\r
-\r
-int arm11_register_commands(struct command_context_s *cmd_ctx);\r
-int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);\r
-int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);\r
-int arm11_quit(void);\r
-\r
-\r
-/* helpers */\r
-void arm11_build_reg_cache(target_t *target);\r
-\r
-\r
-/* internals */\r
-\r
-void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);\r
-void arm11_add_IR (arm11_common_t * arm11, u8 instr, enum tap_state state);\r
-void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, enum tap_state state);\r
-void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state);\r
-u32 arm11_read_DSCR (arm11_common_t * arm11);\r
-void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);\r
-\r
-enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);\r
-\r
-void arm11_run_instr_data_prepare (arm11_common_t * arm11);\r
-void arm11_run_instr_data_finish (arm11_common_t * arm11);\r
-void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);\r
-void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);\r
-void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);\r
-void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);\r
-void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);\r
-void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);\r
-void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);\r
-\r
-\r
-typedef struct arm11_sc7_action_s\r
-{\r
- bool write;\r
- u8 address;\r
- u32 value;\r
-} arm11_sc7_action_t;\r
-\r
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);\r
-void arm11_sc7_clear_bw(arm11_common_t * arm11);\r
-\r
-\r
-\r
-#endif /* ARM11_H */\r
+/***************************************************************************
+ * Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
+ * *
+ * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+#ifndef ARM11_H
+#define ARM11_H
+
+#include "target.h"
+#include "register.h"
+#include "jtag.h"
+
+#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
+
+#define NEW(type, variable, items) \
+ type * variable = calloc(1, sizeof(type) * items)
+
+/* For MinGW use 'I' prefix to print size_t (instead of 'z') */
+/* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */
+
+#if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
+#define ZU "%zu"
+#else
+#define ZU "%Iu"
+#endif
+
+#define ARM11_REGCACHE_MODEREGS 0
+#define ARM11_REGCACHE_FREGS 0
+
+#define ARM11_REGCACHE_COUNT (20 + \
+ 23 * ARM11_REGCACHE_MODEREGS + \
+ 9 * ARM11_REGCACHE_FREGS)
+
+#define ARM11_TAP_DEFAULT TAP_INVALID
+
+
+#define CHECK_RETVAL(action) \
+do { \
+ int __retval = (action); \
+ \
+ if (__retval != ERROR_OK) \
+ { \
+ LOG_DEBUG("error while calling \"" # action "\""); \
+ return __retval; \
+ } \
+ \
+} while (0)
+
+
+struct arm11_register_history
+{
+ uint32_t value;
+ uint8_t valid;
+};
+
+enum arm11_debug_version
+{
+ ARM11_DEBUG_V6 = 0x01,
+ ARM11_DEBUG_V61 = 0x02,
+ ARM11_DEBUG_V7 = 0x03,
+ ARM11_DEBUG_V7_CP14 = 0x04,
+};
+
+struct arm11_common
+{
+ target_t * target; /**< Reference back to the owner */
+
+ /** \name Processor type detection */
+ /*@{*/
+
+ uint32_t device_id; /**< IDCODE readout */
+ uint32_t didr; /**< DIDR readout (debug capabilities) */
+ uint8_t implementor; /**< DIDR Implementor readout */
+
+ size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
+ size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
+
+ enum arm11_debug_version
+ debug_version; /**< ARM debug architecture from DIDR */
+ /*@}*/
+
+ uint32_t last_dscr; /**< Last retrieved DSCR value;
+ Use only for debug message generation */
+
+ bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
+
+ /** \name Shadow registers to save processor state */
+ /*@{*/
+
+ reg_t * reg_list; /**< target register list */
+ uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
+
+ /*@}*/
+
+ struct arm11_register_history
+ reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
+
+ size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
+ size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
+
+ // GA
+ struct reg_cache *core_cache;
+};
+
+
+/**
+ * ARM11 DBGTAP instructions
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
+ */
+enum arm11_instructions
+{
+ ARM11_EXTEST = 0x00,
+ ARM11_SCAN_N = 0x02,
+ ARM11_RESTART = 0x04,
+ ARM11_HALT = 0x08,
+ ARM11_INTEST = 0x0C,
+ ARM11_ITRSEL = 0x1D,
+ ARM11_IDCODE = 0x1E,
+ ARM11_BYPASS = 0x1F,
+};
+
+enum arm11_dscr
+{
+ ARM11_DSCR_CORE_HALTED = 1 << 0,
+ ARM11_DSCR_CORE_RESTARTED = 1 << 1,
+
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
+
+ ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
+ ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
+ ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
+ ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
+ ARM11_DSCR_MODE_SELECT = 1 << 14,
+ ARM11_DSCR_WDTR_FULL = 1 << 29,
+ ARM11_DSCR_RDTR_FULL = 1 << 30,
+};
+
+enum arm11_cpsr
+{
+ ARM11_CPSR_T = 1 << 5,
+ ARM11_CPSR_J = 1 << 24,
+};
+
+enum arm11_sc7
+{
+ ARM11_SC7_NULL = 0,
+ ARM11_SC7_VCR = 7,
+ ARM11_SC7_PC = 8,
+ ARM11_SC7_BVR0 = 64,
+ ARM11_SC7_BCR0 = 80,
+ ARM11_SC7_WVR0 = 96,
+ ARM11_SC7_WCR0 = 112,
+};
+
+struct arm11_reg_state
+{
+ uint32_t def_index;
+ target_t * target;
+};
+
+int arm11_register_commands(struct command_context_s *cmd_ctx);
+
+int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t *value);
+int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value);
+
+
+
+#endif /* ARM11_H */
projects / fw / openocd / blobdiff