change #include "armv4_5_cache.h" to <target/armv4_5_cache.h>

[fw/openocd] / src / target / arm11.h

diff --git a/src/target/arm11.h b/src/target/arm11.h
index a67c33710b7d297853bd390f6aaf6c82f8d5aa72..b118e1c6cd3d7dcd2185e6a11264eade7e0e93f3 100644 (file)
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -23,11 +23,8 @@
 #ifndef ARM11_H
 #define ARM11_H
 
-#include "armv4_5.h"
-#include "arm_dpm.h"
-
-/* TEMPORARY -- till we switch to the shared infrastructure */
-#define ARM11_REGCACHE_COUNT           20
+#include <target/armv4_5.h>
+#include <target/arm_dpm.h>
 
 #define ARM11_TAP_DEFAULT                      TAP_INVALID
 
@@ -41,12 +38,6 @@
                }                               \
        } while (0)
 
-struct arm11_register_history
-{
-       uint32_t                value;
-       uint8_t         valid;
-};
-
 enum arm11_debug_version
 {
        ARM11_DEBUG_V6                  = 0x01,
@@ -58,40 +49,23 @@ enum arm11_debug_version
 struct arm11_common
 {
        struct arm      arm;
-       struct target * target;         /**< Reference back to the owner */
 
        /** Debug module state. */
        struct arm_dpm dpm;
 
-       /** \name Processor type detection */
-       /*@{*/
-
        size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
        size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
+       size_t  free_brps;              /**< Number of breakpoints allocated */
 
-       /*@}*/
-
-       uint32_t                last_dscr;              /**< Last retrieved DSCR value;
-                                                            Use only for debug message generation              */
+       uint32_t dscr;                  /**< Last retrieved DSCR value. */
 
-       bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
-
-       /** \name Shadow registers to save processor state */
-       /*@{*/
-
-       struct reg *    reg_list;                                                       /**< target register list */
-       uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
+       uint32_t saved_rdtr;
+       uint32_t saved_wdtr;
 
-       /*@}*/
+       bool is_rdtr_saved;
+       bool is_wdtr_saved;
 
-       struct arm11_register_history
-               reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
-
-       size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
-       size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
-
-       // GA
-       struct reg_cache *core_cache;
+       bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
 
        struct arm_jtag jtag_info;
 };