change #include "embeddedice.h" to <target/embeddedice.h>

[fw/openocd] / src / target / arm11.h

diff --git a/src/target/arm11.h b/src/target/arm11.h
index cde6c787d014504c69f8c8737acf12b20d10d315..b118e1c6cd3d7dcd2185e6a11264eade7e0e93f3 100644 (file)
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -23,10 +23,8 @@
 #ifndef ARM11_H
 #define ARM11_H
 
-#include "armv4_5.h"
-#include "arm_dpm.h"
-
-#define ARM11_REGCACHE_COUNT           2
+#include <target/armv4_5.h>
+#include <target/arm_dpm.h>
 
 #define ARM11_TAP_DEFAULT                      TAP_INVALID
 
@@ -59,25 +57,15 @@ struct arm11_common
        size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
        size_t  free_brps;              /**< Number of breakpoints allocated */
 
-       uint32_t                last_dscr;              /**< Last retrieved DSCR value;
-                                                            Use only for debug message generation              */
+       uint32_t dscr;                  /**< Last retrieved DSCR value. */
 
        uint32_t saved_rdtr;
+       uint32_t saved_wdtr;
 
        bool is_rdtr_saved;
-       bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
-
-       /** \name Shadow registers to save debug state */
-       /*@{*/
-
-       struct reg *    reg_list;                                                       /**< target register list */
-       uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
+       bool is_wdtr_saved;
 
-       /*@}*/
-
-
-       // GA
-       struct reg_cache *core_cache;
+       bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
 
        struct arm_jtag jtag_info;
 };