} while (0)
-typedef struct arm11_register_history_s
+struct arm11_register_history
{
uint32_t value;
uint8_t valid;
-}arm11_register_history_t;
+};
enum arm11_debug_version
{
ARM11_DEBUG_V7_CP14 = 0x04,
};
-typedef struct arm11_common_s
+struct arm11_common
{
target_t * target; /**< Reference back to the owner */
/** \name Shadow registers to save processor state */
/*@{*/
- reg_t * reg_list; /**< target register list */
+ struct reg * reg_list; /**< target register list */
uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
- arm11_register_history_t
+ struct arm11_register_history
reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
// GA
- reg_cache_t *core_cache;
-} arm11_common_t;
+ struct reg_cache *core_cache;
+};
/**
ARM11_SC7_WCR0 = 112,
};
-typedef struct arm11_reg_state_s
+struct arm11_reg_state
{
uint32_t def_index;
target_t * target;
-} arm11_reg_state_t;
+};
int arm11_register_commands(struct command_context_s *cmd_ctx);
-/* internals */
-
-void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
-void arm11_add_IR (arm11_common_t * arm11, uint8_t instr, tap_state_t state);
-int arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
-void arm11_add_debug_INST (arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state);
-int arm11_read_DSCR (arm11_common_t * arm11, uint32_t *dscr);
-int arm11_write_DSCR (arm11_common_t * arm11, uint32_t dscr);
-
-enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
-
-int arm11_run_instr_data_prepare (arm11_common_t * arm11);
-int arm11_run_instr_data_finish (arm11_common_t * arm11);
-int arm11_run_instr_no_data (arm11_common_t * arm11, uint32_t * opcode, size_t count);
-int arm11_run_instr_no_data1 (arm11_common_t * arm11, uint32_t opcode);
-int arm11_run_instr_data_to_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
-int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
-int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
-int arm11_run_instr_data_from_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
-int arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
-int arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
-
-int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
-int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
-
-/** Used to make a list of read/write commands for scan chain 7
- *
- * Use with arm11_sc7_run()
- */
-typedef struct arm11_sc7_action_s
-{
- bool write; /**< Access mode: true for write, false for read. */
- uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */
- uint32_t value; /**< If write then set this to value to be written.
- In read mode this receives the read value when the
- function returns. */
-} arm11_sc7_action_t;
-
-int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
+int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t *value);
+int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value);
-/* Mid-level helper functions */
-void arm11_sc7_clear_vbw(arm11_common_t * arm11);
-void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value);
-int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result);
#endif /* ARM11_H */