/** \name Shadow registers to save processor state */
/*@{*/
- reg_t * reg_list; /**< target register list */
+ struct reg * reg_list; /**< target register list */
uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
// GA
- reg_cache_t *core_cache;
+ struct reg_cache *core_cache;
};
ARM11_SC7_WCR0 = 112,
};
-typedef struct arm11_reg_state_s
+struct arm11_reg_state
{
uint32_t def_index;
target_t * target;
-} arm11_reg_state_t;
+};
int arm11_register_commands(struct command_context_s *cmd_ctx);