#endif
#include "arm11.h"
+#include "target_type.h"
#if 0
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
-u32 arm11_vcr = 0;
+uint32_t arm11_vcr = 0;
bool arm11_config_memrw_no_increment = false;
bool arm11_config_step_irq_enable = false;
typedef struct arm11_reg_defs_s
{
char * name;
- u32 num;
+ uint32_t num;
int gdb_num;
enum arm11_regtype type;
} arm11_reg_defs_t;
#define ARM11_GDB_REGISTER_COUNT 26
-u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
reg_t arm11_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
-u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
reg_t arm11_gdb_dummy_fps_reg =
{
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
{
FNC_INFO;
- u32 dscr_local_tmp_copy;
+ uint32_t dscr_local_tmp_copy;
if (!dscr)
{
/* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
ARM1136 seems to require this to issue ITR's as well */
- u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
+ uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
/* this executes JTAG queue: */
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
- u32 dscr = arm11_read_DSCR(arm11);
+ uint32_t dscr = arm11_read_DSCR(arm11);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].valid)
- LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
+ LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
if (arm11->reg_history[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
- LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
+ LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
}
else
{
- LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
+ LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
}
}
}
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
- u32 DSCR;
+ uint32_t DSCR;
CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
- LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
+ LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
}
}
scan_field_t chain5_fields[3];
- u8 Ready = 0; /* ignored */
- u8 Valid = 0; /* ignored */
+ uint8_t Ready = 0; /* ignored */
+ uint8_t Valid = 0; /* ignored */
arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
if (arm11->trst_active)
return ERROR_OK;
- u32 dscr;
+ uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
- LOG_DEBUG("DSCR %08x", dscr);
+ LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
CHECK_RETVAL(arm11_check_init(arm11, &dscr));
{
arm11_common_t * arm11 = target->arch_info;
- LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
- Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
+ LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
+ Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name,
R(CPSR),
R(PC));
}
/* target request support */
-int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
+int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
{
FNC_INFO_NOTIMPLEMENTED;
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+ Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
if (target->state == TARGET_UNKNOWN)
{
CHECK_RETVAL(jtag_execute_queue());
- u32 dscr;
+ uint32_t dscr;
while (1)
{
return ERROR_OK;
}
-int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+ Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
if (target->state != TARGET_HALTED)
if (!current)
R(PC) = address;
- LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
arm11_sc7_clear_vbw(arm11);
{
if (bp->address == R(PC))
{
- LOG_DEBUG("must step over %08x", bp->address);
+ LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
arm11_step(target, 1, 0, 0);
break;
}
arm11_sc7_run(arm11, brp, asizeof(brp));
- LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
+ LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
brp_num++;
}
while (1)
{
- u32 dscr;
+ uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
- LOG_DEBUG("DSCR %08x", dscr);
+ LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
if (dscr & ARM11_DSCR_CORE_RESTARTED)
break;
return ERROR_OK;
}
-int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
FNC_INFO;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+ Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
if (target->state != TARGET_HALTED)
{
if (!current)
R(PC) = address;
- LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
- u32 next_instruction;
+ uint32_t next_instruction;
CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
while (1)
{
- u32 dscr;
+ uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
- LOG_DEBUG("DSCR %08x", dscr);
+ LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
(ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
#if 0
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+ Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
/* deassert reset lines */
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
+ /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
FNC_INFO;
return ERROR_TARGET_NOT_HALTED;
}
- LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
+ LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
arm11_common_t * arm11 = target->arch_info;
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
- u32 res;
+ uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
- u32 res;
+ uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
- u16 svalue = res;
- memcpy(buffer + count * sizeof(u16), &svalue, sizeof(u16));
+ uint16_t svalue = res;
+ memcpy(buffer + count * sizeof(uint16_t), &svalue, sizeof(uint16_t));
}
break;
case 4:
{
- u32 instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
- /** \todo TODO: buffer cast to u32* causes alignment warnings */
- u32 *words = (u32 *)buffer;
+ uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
+ /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+ uint32_t *words = (uint32_t *)buffer;
/* LDC p14,c5,[R0],#4 */
/* LDC p14,c5,[R0] */
return ERROR_OK;
}
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
FNC_INFO;
return ERROR_TARGET_NOT_HALTED;
}
- LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
+ LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
arm11_common_t * arm11 = target->arch_info;
for (size_t i = 0; i < count; i++)
{
- u16 value;
- memcpy(&value, buffer + count * sizeof(u16), sizeof(u16));
+ uint16_t value;
+ memcpy(&value, buffer + count * sizeof(uint16_t), sizeof(uint16_t));
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
}
case 4: {
- u32 instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
+ uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
- /** \todo TODO: buffer cast to u32* causes alignment warnings */
- u32 *words = (u32*)buffer;
+ /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+ uint32_t *words = (uint32_t*)buffer;
if (!arm11_config_memwrite_burst)
{
/* r0 verification */
if (!arm11_config_memrw_no_increment)
{
- u32 r0;
+ uint32_t r0;
/* MCR p14,0,R0,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
if (address + size * count != r0)
{
- LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
+ LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
if (arm11_config_memwrite_burst)
LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
+int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
FNC_INFO;
* fallback code will read data from the target and calculate the CRC on the
* host.
*/
-int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
{
return ERROR_FAIL;
}
// HACKHACKHACK - FIXME mode/state
/* target algorithm support */
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
- int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
+ int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info)
{
arm11_common_t *arm11 = target->arch_info;
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
- u32 context[16];
- u32 cpsr;
+ uint32_t context[16];
+ uint32_t cpsr;
int exit_breakpoint_size = 0;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
// Save regs
for (size_t i = 0; i < 16; i++)
{
- context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
- LOG_DEBUG("Save %zi: 0x%x",i,context[i]);
+ context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
+ LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
}
- cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
- LOG_DEBUG("Save CPSR: 0x%x", cpsr);
+ cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
+ LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
for (int i = 0; i < num_mem_params; i++)
{
if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
{
- LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
+ LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
buf_get_u32(arm11->reg_list[15].value, 0, 32));
retval = ERROR_TARGET_TIMEOUT;
goto del_breakpoint;
// Restore context
for (size_t i = 0; i < 16; i++)
{
- LOG_DEBUG("restoring register %s with value 0x%8.8x",
+ LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
arm11->reg_list[i].name, context[i]);
- arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
+ arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
}
- LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
- arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
+ LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
+ arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
// arm11->core_state = core_state;
// arm11->core_mode = core_mode;
arm11->target = target;
- if (target->tap==NULL)
+ if (target->tap == NULL)
return ERROR_FAIL;
if (target->tap->ir_length != 5)
arm11->free_brps = arm11->brp;
arm11->free_wrps = arm11->wrp;
- LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
+ LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
arm11->device_id,
- arm11->implementor,
+ (int)(arm11->implementor),
arm11->didr);
/* as a side-effect this reads DSCR and thus
}
/** Change a value in the register cache */
-int arm11_set_reg(reg_t *reg, u8 *buf)
+int arm11_set_reg(reg_t *reg, uint8_t *buf)
{
FNC_INFO;
r->name = rd->name;
r->size = 32;
- r->value = (u8 *)(arm11->reg_values + i);
+ r->value = (uint8_t *)(arm11->reg_values + i);
r->dirty = 0;
r->valid = 0;
r->bitfield_desc = NULL;
return ERROR_COMMAND_SYNTAX_ERROR;
}
- LOG_INFO("VCR 0x%08X", arm11_vcr);
+ LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
return ERROR_OK;
}
-const u32 arm11_coproc_instruction_limits[] =
+const uint32_t arm11_coproc_instruction_limits[] =
{
15, /* coprocessor */
7, /* opcode 1 */
jtag_tap_t * tap;
target_t * t;
- tap = jtag_TapByString(arg);
+ tap = jtag_tap_by_string(arg);
if (!tap)
return 0;
return ERROR_TARGET_NOT_HALTED;
}
- u32 values[6];
+ uint32_t values[6];
for (size_t i = 0; i < (read ? 5 : 6); i++)
{
if (values[i] > arm11_coproc_instruction_limits[i])
{
- LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
- (long)(i + 2), arm11_coproc_instruction_limits[i],
+ LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
+ (long)(i + 2),
+ arm11_coproc_instruction_limits[i],
read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
}
}
- u32 instr = 0xEE000010 |
+ uint32_t instr = 0xEE000010 |
(values[0] << 8) |
(values[1] << 21) |
(values[2] << 16) |
if (read)
{
- u32 result;
+ uint32_t result;
arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
- LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
- values[0], values[1], values[2], values[3], values[4], result, result);
+ LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
+ (int)(values[0]),
+ (int)(values[1]),
+ (int)(values[2]),
+ (int)(values[3]),
+ (int)(values[4]), result, result);
}
else
{
arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
- LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
- values[0], values[1],
- values[5],
- values[2], values[3], values[4]);
+ LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
+ (int)(values[0]), (int)(values[1]),
+ values[5],
+ (int)(values[2]), (int)(values[3]), (int)(values[4]));
}
arm11_run_instr_data_finish(arm11);
command_t * top_cmd = NULL;
- RC_TOP( "arm11", "arm11 specific commands",
+ RC_TOP("arm11", "arm11 specific commands",
- RC_TOP( "memwrite", "Control memory write transfer mode",
+ RC_TOP("memwrite", "Control memory write transfer mode",
- RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
+ RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
memwrite_burst)
- RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
+ RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
) /* memwrite */
- RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
+ RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
- RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
+ RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
step_irq_enable)
- RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
+ RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
arm11_handle_vcr)
- RC_FINAL( "mrc", "Read Coprocessor register",
+ RC_FINAL("mrc", "Read Coprocessor register",
arm11_handle_mrc)
- RC_FINAL( "mcr", "Write Coprocessor register",
+ RC_FINAL("mcr", "Write Coprocessor register",
arm11_handle_mcr)
) /* arm11 */
projects / fw / openocd / blobdiff