#include "config.h"
#endif
-#include "arm11.h"
+#include "etm.h"
+#include "breakpoints.h"
#include "arm11_dbgtap.h"
-#include "armv4_5.h"
#include "arm_simulator.h"
#include "time_support.h"
#include "target_type.h"
+#include "algorithm.h"
+#include "register.h"
#if 0
static bool arm11_config_step_irq_enable = false;
static bool arm11_config_hardware_step = false;
-static int arm11_regs_arch_type = -1;
-
enum arm11_regtype
{
ARM11_REGISTER_CORE,
.valid = 1,
.size = 96,
.arch_info = NULL,
- .arch_type = 0,
};
static uint8_t arm11_gdb_dummy_fps_value[4];
.valid = 1,
.size = 32,
.arch_info = NULL,
- .arch_type = 0,
};
int retval;
FNC_INFO;
- for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
+ for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
{
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
else
{
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
arm11_record_register_history(arm11);
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
}
- CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
/* resume */
return arm11_write_memory(target, address, 4, count, buffer);
}
-/* here we have nothing target specific to contribute, so we fail and then the
- * fallback code will read data from the target and calculate the CRC on the
- * host.
- */
-static int arm11_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t* checksum)
-{
- return ERROR_FAIL;
-}
-
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
*/
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
arm11_set_reg(reg,reg_params[i].value);
// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+ retval = ERROR_INVALID_ARGUMENTS;
+ goto del_breakpoint;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+ retval = ERROR_INVALID_ARGUMENTS;
+ goto del_breakpoint;
}
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
- arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
return ERROR_OK;
}
+static const struct reg_arch_type arm11_reg_type = {
+ .get = arm11_get_reg,
+ .set = arm11_set_reg,
+};
+
static int arm11_build_reg_cache(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
- if (arm11_regs_arch_type == -1)
- arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
-
register_init_dummy(&arm11_gdb_dummy_fp_reg);
register_init_dummy(&arm11_gdb_dummy_fps_reg);
size_t i;
/* Not very elegant assertion */
- if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
- ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
+ if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
+ ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
- LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
+ LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, ARRAY_SIZE(arm11->reg_values), ARRAY_SIZE(arm11_reg_defs), ARM11_RC_MAX);
exit(-1);
}
r->value = (uint8_t *)(arm11->reg_values + i);
r->dirty = 0;
r->valid = 0;
- r->arch_type = arm11_regs_arch_type;
+ r->type = &arm11_reg_type;
r->arch_info = rs;
rs->def_index = i;
static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
{
- if (argc == 0)
+ if (CMD_ARGC == 0)
{
LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
return ERROR_OK;
}
- if (argc != 1)
+ if (CMD_ARGC != 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- switch (args[0][0])
+ switch (CMD_ARGV[0][0])
{
case '0': /* 0 */
case 'f': /* false */
COMMAND_HANDLER(arm11_handle_vcr)
{
- switch (argc) {
+ switch (CMD_ARGC) {
case 0:
break;
case 1:
- COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
struct command *top_cmd, *mw_cmd;
+ armv4_5_register_commands(cmd_ctx);
+
top_cmd = register_command(cmd_ctx, NULL, "arm11",
NULL, COMMAND_ANY, NULL);
.bulk_write_memory = arm11_bulk_write_memory,
- .checksum_memory = arm11_checksum_memory,
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
.add_breakpoint = arm11_add_breakpoint,
.remove_breakpoint = arm11_remove_breakpoint,
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