* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the
- * Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef ARM_H
-#define ARM_H
+
+#ifndef OPENOCD_TARGET_ARM_H
+#define OPENOCD_TARGET_ARM_H
#include <helper/command.h>
#include "target.h"
ARM_MODE_FIQ = 17,
ARM_MODE_IRQ = 18,
ARM_MODE_SVC = 19,
+ ARM_MODE_MON = 22,
ARM_MODE_ABT = 23,
- ARM_MODE_MON = 26,
ARM_MODE_UND = 27,
+ ARM_MODE_1176_MON = 28,
ARM_MODE_SYS = 31,
- ARM_MODE_THREAD,
- ARM_MODE_USER_THREAD,
- ARM_MODE_HANDLER,
+ ARM_MODE_THREAD = 0,
+ ARM_MODE_USER_THREAD = 1,
+ ARM_MODE_HANDLER = 2,
+
+ /* shift left 4 bits for armv8 64 */
+ ARMV8_64_EL0T = 0x0F,
+ ARMV8_64_EL1T = 0x4F,
+ ARMV8_64_EL1H = 0x5F,
+ ARMV8_64_EL2T = 0x8F,
+ ARMV8_64_EL2H = 0x9F,
+ ARMV8_64_EL3T = 0xCF,
+ ARMV8_64_EL3H = 0xDF,
ARM_MODE_ANY = -1
};
ARM_STATE_THUMB,
ARM_STATE_JAZELLE,
ARM_STATE_THUMB_EE,
+ ARM_STATE_AARCH64,
};
-extern const char *arm_state_strings[];
-
#define ARM_COMMON_MAGIC 0x0A450A45
/**
int common_magic;
struct reg_cache *core_cache;
- /** Handle to the CPSR; valid in all core modes. */
+ /** Handle to the PC; valid in all core modes. */
+ struct reg *pc;
+
+ /** Handle to the CPSR/xPSR; valid in all core modes. */
struct reg *cpsr;
/** Handle to the SPSR; valid only in core modes with an SPSR. */
/** Flag reporting unavailability of the BKPT instruction. */
bool is_armv4;
+ /** Flag reporting armv6m based core. */
+ bool is_armv6m;
+
/** Flag reporting whether semihosting is active. */
bool is_semihosting;
+ /** Flag reporting whether semihosting fileio is active. */
+ bool is_semihosting_fileio;
+
+ /** Flag reporting whether semihosting fileio operation is active. */
+ bool semihosting_hit_fileio;
+
+ /** Current semihosting operation. */
+ int semihosting_op;
+
+ /** Current semihosting result. */
+ int semihosting_result;
+
/** Value to be returned by semihosting SYS_ERRNO request. */
int semihosting_errno;
+ int (*setup_semihosting)(struct target *target, int enable);
+
+ /** Semihosting command line. */
+ char *semihosting_cmdline;
+
/** Backpointer to the target. */
struct target *target;
int (*read_core_reg)(struct target *target, struct reg *reg,
int num, enum arm_mode mode);
int (*write_core_reg)(struct target *target, struct reg *reg,
- int num, enum arm_mode mode, uint32_t value);
+ int num, enum arm_mode mode, uint8_t *value);
/** Read coprocessor register. */
int (*mrc)(struct target *target, int cpnum,
uint32_t value);
void *arch_info;
+
+ /** For targets conforming to ARM Debug Interface v5,
+ * this handle references the Debug Access Port (DAP)
+ * used to make requests to the target.
+ */
+ struct adiv5_dap *dap;
};
/** Convert target handle to generic ARM target state handle. */
static inline struct arm *target_to_arm(struct target *target)
{
+ assert(target != NULL);
return target->arch_info;
}
static inline bool is_arm(struct arm *arm)
{
- return arm && arm->common_magic == ARM_COMMON_MAGIC;
+ assert(arm != NULL);
+ return arm->common_magic == ARM_COMMON_MAGIC;
}
struct arm_algorithm {
int num;
enum arm_mode mode;
struct target *target;
- struct arm *armv4_5_common;
- uint32_t value;
+ struct arm *arm;
+ uint8_t value[8];
};
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
+struct reg_cache *armv8_build_reg_cache(struct target *target);
extern const struct command_registration arm_command_handlers[];
int arm_arch_state(struct target *target);
int arm_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class);
+int armv8_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class);
int arm_init_arch_info(struct target *target, struct arm *arm);
int armv4_5_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
int timeout_ms, void *arch_info);
int armv4_5_run_algorithm_inner(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int timeout_ms, void *arch_info));
int arm_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum);
+ target_addr_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank);
+ target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value);
void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
-
-void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
+struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
extern struct reg arm_gdb_dummy_fp_reg;
extern struct reg arm_gdb_dummy_fps_reg;
-#endif /* ARM_H */
+#endif /* OPENOCD_TARGET_ARM_H */
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