target/armv7m: rework Cortex-M register handling part 1

[fw/openocd] / src / target / arm.h

diff --git a/src/target/arm.h b/src/target/arm.h
index bf0d9327e1f908c29de0a1637a60a9943ff93b2f..d97a95edf934a0e6fbeeb102e32b62cec7bfb658 100644 (file)
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -47,12 +47,16 @@
  *   on for example ARM7TDMI cores.
  * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
  *   three more registers are shadowed for "Secure Monitor" mode.
+ * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
+ *   and also security extensions. Additional shadowed registers for
+ *   "Secure Monitor" and "Hypervisor" modes.
  * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
  *   which only shadows SP.
  */
 enum arm_core_type {
        ARM_CORE_TYPE_STD = -1,
        ARM_CORE_TYPE_SEC_EXT = 1,
+       ARM_CORE_TYPE_VIRT_EXT,
        ARM_CORE_TYPE_M_PROFILE,
 };
 
@@ -76,6 +80,7 @@ enum arm_mode {
        ARM_MODE_SVC = 19,
        ARM_MODE_MON = 22,
        ARM_MODE_ABT = 23,
+       ARM_MODE_HYP = 26,
        ARM_MODE_UND = 27,
        ARM_MODE_1176_MON = 28,
        ARM_MODE_SYS = 31,
@@ -192,6 +197,9 @@ struct arm {
        /** Flag reporting armv6m based core. */
        bool is_armv6m;
 
+       /** Flag reporting armv8m based core. */
+       bool is_armv8m;
+
        /** Floating point or VFP version, 0 if disabled. */
        int arm_vfp_version;
 
@@ -267,6 +275,8 @@ struct arm_reg {
 };
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
+void arm_free_reg_cache(struct arm *arm);
+
 struct reg_cache *armv8_build_reg_cache(struct target *target);
 
 extern const struct command_registration arm_command_handlers[];