* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the
- * Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef ARM_H
-#define ARM_H
+#ifndef OPENOCD_TARGET_ARM_H
+#define OPENOCD_TARGET_ARM_H
#include <helper/command.h>
#include "target.h"
ARM_MODE_FIQ = 17,
ARM_MODE_IRQ = 18,
ARM_MODE_SVC = 19,
+ ARM_MODE_MON = 22,
ARM_MODE_ABT = 23,
- ARM_MODE_MON = 26,
ARM_MODE_UND = 27,
+ ARM_MODE_1176_MON = 28,
ARM_MODE_SYS = 31,
ARM_MODE_THREAD = 0,
/** Handle to the PC; valid in all core modes. */
struct reg *pc;
- /** Handle to the CPSR; valid in all core modes. */
+ /** Handle to the CPSR/xPSR; valid in all core modes. */
struct reg *cpsr;
/** Handle to the SPSR; valid only in core modes with an SPSR. */
int (*read_core_reg)(struct target *target, struct reg *reg,
int num, enum arm_mode mode);
int (*write_core_reg)(struct target *target, struct reg *reg,
- int num, enum arm_mode mode, uint32_t value);
+ int num, enum arm_mode mode, uint8_t *value);
/** Read coprocessor register. */
int (*mrc)(struct target *target, int cpnum,
enum arm_mode mode;
struct target *target;
struct arm *arm;
- uint32_t value;
+ uint8_t value[4];
};
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
extern struct reg arm_gdb_dummy_fp_reg;
extern struct reg arm_gdb_dummy_fps_reg;
-#endif /* ARM_H */
+#endif /* OPENOCD_TARGET_ARM_H */