* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the
- * Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
***************************************************************************/
/**
#include <jtag/swd.h>
-/* YUK! - but this is currently a global.... */
-extern struct jtag_interface *jtag_interface;
static bool do_sync;
static void swd_finish_read(struct adiv5_dap *dap)
{
- const struct swd_driver *swd = jtag_interface->swd;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
if (dap->last_read != NULL) {
swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
dap->last_read = NULL;
static void swd_clear_sticky_errors(struct adiv5_dap *dap)
{
- const struct swd_driver *swd = jtag_interface->swd;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
assert(swd);
swd->write_reg(swd_cmd(false, false, DP_ABORT),
static int swd_run_inner(struct adiv5_dap *dap)
{
- const struct swd_driver *swd = jtag_interface->swd;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
int retval;
retval = swd->run();
static int swd_connect(struct adiv5_dap *dap)
{
- uint32_t dpidr;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
+ uint32_t dpidr = 0xdeadbeef;
int status;
/* FIXME validate transport config ... is the
* MUST READ DPIDR
*/
- /* Note, debugport_init() does setup too */
- jtag_interface->swd->switch_seq(JTAG_TO_SWD);
+ /* Check if we should reset srst already when connecting, but not if reconnecting. */
+ if (!dap->do_reconnect) {
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
- /* Clear link state, including the SELECT cache. */
- dap->do_reconnect = false;
- dap->select = DP_SELECT_INVALID;
+ if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
+ if (jtag_reset_config & RESET_SRST_NO_GATING)
+ adapter_assert_reset();
+ else
+ LOG_WARNING("\'srst_nogate\' reset_config option is required");
+ }
+ }
- swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
- /* force clear all sticky faults */
- swd_clear_sticky_errors(dap);
+ int64_t timeout = timeval_ms() + 500;
- status = swd_run_inner(dap);
+ do {
+ /* Note, debugport_init() does setup too */
+ swd->switch_seq(JTAG_TO_SWD);
- if (status == ERROR_OK) {
- LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
+ /* Clear link state, including the SELECT cache. */
dap->do_reconnect = false;
- } else
- dap->do_reconnect = true;
+ dap_invalidate_cache(dap);
+
+ status = swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
+ if (status == ERROR_OK) {
+ status = swd_run_inner(dap);
+ if (status == ERROR_OK)
+ break;
+ }
+
+ alive_sleep(1);
+
+ } while (timeval_ms() < timeout);
+
+ if (status != ERROR_OK) {
+ LOG_ERROR("Error connecting DP: cannot read IDR");
+ return status;
+ }
+
+ LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
+
+ do {
+ dap->do_reconnect = false;
+
+ /* force clear all sticky faults */
+ swd_clear_sticky_errors(dap);
+
+ status = swd_run_inner(dap);
+ if (status != ERROR_WAIT)
+ break;
+
+ alive_sleep(10);
+
+ } while (timeval_ms() < timeout);
+
+ /* IHI 0031E B4.3.2:
+ * "A WAIT response must not be issued to the ...
+ * ... writes to the ABORT register"
+ * swd_clear_sticky_errors() writes to the ABORT register only.
+ *
+ * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
+ * in a corner case. Just try if ABORT resolves the problem.
+ */
+ if (status == ERROR_WAIT) {
+ LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
+
+ dap->do_reconnect = false;
+
+ swd->write_reg(swd_cmd(false, false, DP_ABORT),
+ DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
+ status = swd_run_inner(dap);
+ }
+
+ if (status == ERROR_OK)
+ status = dap_dp_init(dap);
return status;
}
+static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
+{
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
+ assert(swd);
+
+ return swd->switch_seq(seq);
+}
+
static inline int check_sync(struct adiv5_dap *dap)
{
return do_sync ? swd_run_inner(dap) : ERROR_OK;
static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
{
- const struct swd_driver *swd = jtag_interface->swd;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
assert(swd);
swd->write_reg(swd_cmd(false, false, DP_ABORT),
}
/** Select the DP register bank matching bits 7:4 of reg. */
-static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
+static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
{
/* Only register address 4 is banked. */
if ((reg & 0xf) != 4)
- return;
+ return ERROR_OK;
uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
uint32_t sel = select_dp_bank
| (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
if (sel == dap->select)
- return;
+ return ERROR_OK;
dap->select = sel;
- swd_queue_dp_write(dap, DP_SELECT, sel);
+ int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
+ if (retval != ERROR_OK)
+ dap->select = DP_SELECT_INVALID;
+
+ return retval;
}
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
- const struct swd_driver *swd = jtag_interface->swd;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
assert(swd);
int retval = swd_check_reconnect(dap);
if (retval != ERROR_OK)
return retval;
- swd_queue_dp_bankselect(dap, reg);
+ retval = swd_queue_dp_bankselect(dap, reg);
+ if (retval != ERROR_OK)
+ return retval;
+
swd->read_reg(swd_cmd(true, false, reg), data, 0);
return check_sync(dap);
static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
- const struct swd_driver *swd = jtag_interface->swd;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
assert(swd);
int retval = swd_check_reconnect(dap);
return retval;
swd_finish_read(dap);
- swd_queue_dp_bankselect(dap, reg);
+ if (reg == DP_SELECT) {
+ dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
+
+ swd->write_reg(swd_cmd(false, false, reg), data, 0);
+
+ retval = check_sync(dap);
+ if (retval != ERROR_OK)
+ dap->select = DP_SELECT_INVALID;
+
+ return retval;
+ }
+
+ retval = swd_queue_dp_bankselect(dap, reg);
+ if (retval != ERROR_OK)
+ return retval;
+
swd->write_reg(swd_cmd(false, false, reg), data, 0);
return check_sync(dap);
}
/** Select the AP register bank matching bits 7:4 of reg. */
-static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
+static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
{
struct adiv5_dap *dap = ap->dap;
uint32_t sel = ((uint32_t)ap->ap_num << 24)
| (dap->select & DP_SELECT_DPBANK);
if (sel == dap->select)
- return;
+ return ERROR_OK;
dap->select = sel;
- swd_queue_dp_write(dap, DP_SELECT, sel);
+ int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
+ if (retval != ERROR_OK)
+ dap->select = DP_SELECT_INVALID;
+
+ return retval;
}
static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
uint32_t *data)
{
- const struct swd_driver *swd = jtag_interface->swd;
- assert(swd);
-
struct adiv5_dap *dap = ap->dap;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
+ assert(swd);
int retval = swd_check_reconnect(dap);
if (retval != ERROR_OK)
return retval;
- swd_queue_ap_bankselect(ap, reg);
+ retval = swd_queue_ap_bankselect(ap, reg);
+ if (retval != ERROR_OK)
+ return retval;
+
swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
dap->last_read = data;
static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
uint32_t data)
{
- const struct swd_driver *swd = jtag_interface->swd;
- assert(swd);
-
struct adiv5_dap *dap = ap->dap;
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
+ assert(swd);
int retval = swd_check_reconnect(dap);
if (retval != ERROR_OK)
return retval;
swd_finish_read(dap);
- swd_queue_ap_bankselect(ap, reg);
+ retval = swd_queue_ap_bankselect(ap, reg);
+ if (retval != ERROR_OK)
+ return retval;
+
swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
return check_sync(dap);
return swd_run_inner(dap);
}
+/** Put the SWJ-DP back to JTAG mode */
+static void swd_quit(struct adiv5_dap *dap)
+{
+ const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
+
+ swd->switch_seq(SWD_TO_JTAG);
+ /* flush the queue before exit */
+ swd->run();
+}
+
const struct dap_ops swd_dap_ops = {
+ .connect = swd_connect,
+ .send_sequence = swd_send_sequence,
.queue_dp_read = swd_queue_dp_read,
.queue_dp_write = swd_queue_dp_write,
.queue_ap_read = swd_queue_ap_read,
.queue_ap_write = swd_queue_ap_write,
.queue_ap_abort = swd_queue_ap_abort,
.run = swd_run,
+ .quit = swd_quit,
};
-/*
- * This represents the bits which must be sent out on TMS/SWDIO to
- * switch a DAP implemented using an SWJ-DP module into SWD mode.
- * These bits are stored (and transmitted) LSB-first.
- *
- * See the DAP-Lite specification, section 2.2.5 for information
- * about making the debug link select SWD or JTAG. (Similar info
- * is in a few other ARM documents.)
- */
-static const uint8_t jtag2swd_bitseq[] = {
- /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
- * putting both JTAG and SWD logic into reset state.
- */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- /* Switching sequence enables SWD and disables JTAG
- * NOTE: bits in the DP's IDCODE may expose the need for
- * an old/obsolete/deprecated sequence (0xb6 0xed).
- */
- 0x9e, 0xe7,
- /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
- * putting both JTAG and SWD logic into reset state.
- */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-};
-
-/**
- * Put the debug link into SWD mode, if the target supports it.
- * The link's initial mode may be either JTAG (for example,
- * with SWJ-DP after reset) or SWD.
- *
- * @param target Enters SWD mode (if possible).
- *
- * Note that targets using the JTAG-DP do not support SWD, and that
- * some targets which could otherwise support it may have have been
- * configured to disable SWD signaling
- *
- * @return ERROR_OK or else a fault code.
- */
-int dap_to_swd(struct target *target)
-{
- struct arm *arm = target_to_arm(target);
- int retval;
-
- if (!arm->dap) {
- LOG_ERROR("SWD mode is not available");
- return ERROR_FAIL;
- }
-
- LOG_DEBUG("Enter SWD mode");
-
- /* REVISIT it's ugly to need to make calls to a "jtag"
- * subsystem if the link may not be in JTAG mode...
- */
-
- retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
- jtag2swd_bitseq, TAP_INVALID);
- if (retval == ERROR_OK)
- retval = jtag_execute_queue();
-
- /* set up the DAP's ops vector for SWD mode. */
- arm->dap->ops = &swd_dap_ops;
-
- return retval;
-}
-
static const struct command_registration swd_commands[] = {
{
/*
.mode = COMMAND_ANY,
.help = "SWD command group",
.chain = swd_commands,
+ .usage = "",
},
COMMAND_REGISTRATION_DONE
};
static int swd_select(struct command_context *ctx)
{
+ /* FIXME: only place where global 'adapter_driver' is still needed */
+ extern struct adapter_driver *adapter_driver;
+ const struct swd_driver *swd = adapter_driver->swd_ops;
int retval;
retval = register_commands(ctx, NULL, swd_handlers);
-
if (retval != ERROR_OK)
return retval;
- const struct swd_driver *swd = jtag_interface->swd;
-
/* be sure driver is in SWD mode; start
* with hardware default TRN (1), it can be changed later
*/
return retval;
}
- /* force DAP into SWD mode (not JTAG) */
- /*retval = dap_to_swd(target);*/
-
- if (ctx->current_target) {
- /* force DAP into SWD mode (not JTAG) */
- struct target *target = get_current_target(ctx);
- retval = dap_to_swd(target);
- }
-
return retval;
}
static int swd_init(struct command_context *ctx)
{
- struct target *target = get_current_target(ctx);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
- /* Force the DAP's ops vector for SWD mode.
- * messy - is there a better way? */
- arm->dap->ops = &swd_dap_ops;
-
- return swd_connect(dap);
+ /* nothing done here, SWD is initialized
+ * together with the DAP */
+ return ERROR_OK;
}
static struct transport swd_transport = {