checkpatch: treat jenkins as valid email

[fw/openocd] / src / target / aarch64.h

diff --git a/src/target/aarch64.h b/src/target/aarch64.h
index 513f06d183d264908420fec4a969a12e0aa5517d..2721fe747dbac4c9ae6d071bf220aca7197d43b3 100644 (file)
--- a/src/target/aarch64.h
+++ b/src/target/aarch64.h
@@ -1,27 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2015 by David Ung                                       *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
  ***************************************************************************/
 
-#ifndef AARCH64_H
-#define AARCH64_H
+#ifndef OPENOCD_TARGET_AARCH64_H
+#define OPENOCD_TARGET_AARCH64_H
 
 #include "armv8.h"
 
-#define AARCH64_COMMON_MAGIC 0x411fc082
+#define AARCH64_COMMON_MAGIC 0x41413634U
 
 #define CPUDBG_CPUID   0xD00
 #define CPUDBG_CTYPR   0xD04
@@ -36,37 +24,40 @@
 
 #define AARCH64_PADDRDBG_CPU_SHIFT 13
 
+enum aarch64_isrmasking_mode {
+       AARCH64_ISRMASK_OFF,
+       AARCH64_ISRMASK_ON,
+};
+
 struct aarch64_brp {
        int used;
        int type;
        target_addr_t value;
        uint32_t control;
-       uint8_t BRPn;
+       uint8_t brpn;
 };
 
 struct aarch64_common {
-       int common_magic;
+       unsigned int common_magic;
 
-       /* Context information */
-       uint32_t cpudbg_dscr;
+       struct armv8_common armv8_common;
 
+       /* Context information */
        uint32_t system_control_reg;
        uint32_t system_control_reg_curr;
 
-       enum arm_mode curr_mode;
-
-
        /* Breakpoint register pairs */
        int brp_num_context;
        int brp_num;
        int brp_num_available;
        struct aarch64_brp *brp_list;
 
-       /* Use aarch64_read_regs_through_mem for fast register reads */
-       int fast_reg_read;
-
-       struct armv8_common armv8_common;
+       /* Watchpoint register pairs */
+       int wp_num;
+       int wp_num_available;
+       struct aarch64_brp *wp_list;
 
+       enum aarch64_isrmasking_mode isrmasking_mode;
 };
 
 static inline struct aarch64_common *
@@ -75,4 +66,4 @@ target_to_aarch64(struct target *target)
        return container_of(target->arch_info, struct aarch64_common, armv8_common.arm);
 }
 
-#endif /* AARCH64_H */
+#endif /* OPENOCD_TARGET_AARCH64_H */