#include "target_type.h"
#include "armv8_opcodes.h"
#include "armv8_cache.h"
+#include "arm_coresight.h"
#include "arm_semihosting.h"
#include "jtag/interface.h"
#include "smp.h"
/* Write to memory mapped registers directly with no cache or mmu handling */
static int aarch64_dap_write_memap_register_u32(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t value)
{
int retval;
LOG_DEBUG("target %s exc %i", target_name(target), exc_target);
- while (head != NULL) {
+ while (head) {
struct target *curr = head->target;
struct armv8_common *armv8 = target_to_armv8(curr);
head = head->next;
LOG_DEBUG("target %s prepared", target_name(curr));
- if (first == NULL)
+ if (!first)
first = curr;
}
if (curr->state == TARGET_HALTED)
continue;
/* remember the gdb_service->target */
- if (curr->gdb_service != NULL)
+ if (curr->gdb_service)
gdb_target = curr->gdb_service->target;
/* skip it */
if (curr == gdb_target)
}
/* after all targets were updated, poll the gdb serving target */
- if (gdb_target != NULL && gdb_target != target)
+ if (gdb_target && gdb_target != target)
aarch64_poll(gdb_target);
return ERROR_OK;
break;
}
/* remember the first valid target in the group */
- if (first == NULL)
+ if (!first)
first = curr;
}
if (retval != ERROR_OK)
return retval;
- if (first != NULL)
+ if (first)
retval = aarch64_do_restart_one(first, RESTART_LAZY);
if (retval != ERROR_OK) {
LOG_DEBUG("error restarting target %s", target_name(first));
/* Examine debug reason */
armv8_dpm_report_dscr(dpm, dscr);
- /* save address of instruction that triggered the watchpoint? */
+ /* save the memory address that triggered the watchpoint */
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
uint32_t tmp;
- uint64_t wfar = 0;
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_WFAR1,
- &tmp);
+ armv8->debug_base + CPUV8_DBG_EDWAR0, &tmp);
if (retval != ERROR_OK)
return retval;
- wfar = tmp;
- wfar = (wfar << 32);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_WFAR0,
- &tmp);
- if (retval != ERROR_OK)
- return retval;
- wfar |= tmp;
- armv8_dpm_report_wfar(&armv8->dpm, wfar);
+ target_addr_t edwar = tmp;
+
+ /* EDWAR[63:32] has unknown content in aarch32 state */
+ if (core_state == ARM_STATE_AARCH64) {
+ retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_EDWAR1, &tmp);
+ if (retval != ERROR_OK)
+ return retval;
+ edwar |= ((target_addr_t)tmp) << 32;
+ }
+
+ armv8->dpm.wp_addr = edwar;
}
retval = armv8_dpm_read_current_registers(&armv8->dpm);
bpt_value = brp_list[brp_i].value;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
(uint32_t)(bpt_value & 0xFFFFFFFF));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
(uint32_t)(bpt_value >> 32));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
brp_list[brp_i].value = (breakpoint->asid);
brp_list[brp_i].control = control;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
int retval = ERROR_FAIL;
int brp_1 = 0; /* holds the contextID pair */
int brp_2 = 0; /* holds the IVA pair */
- uint32_t control_CTX, control_IVA;
- uint8_t CTX_byte_addr_select = 0x0F;
- uint8_t IVA_byte_addr_select = 0x0F;
- uint8_t CTX_machmode = 0x03;
- uint8_t IVA_machmode = 0x01;
+ uint32_t control_ctx, control_iva;
+ uint8_t ctx_byte_addr_select = 0x0F;
+ uint8_t iva_byte_addr_select = 0x0F;
+ uint8_t ctx_machmode = 0x03;
+ uint8_t iva_machmode = 0x01;
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
struct aarch64_brp *brp_list = aarch64->brp_list;
(brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < aarch64->brp_num))
brp_1++;
- printf("brp(CTX) found num: %d\n", brp_1);
+ LOG_DEBUG("brp(CTX) found num: %d", brp_1);
if (brp_1 >= aarch64->brp_num) {
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
return ERROR_FAIL;
(brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < aarch64->brp_num))
brp_2++;
- printf("brp(IVA) found num: %d\n", brp_2);
+ LOG_DEBUG("brp(IVA) found num: %d", brp_2);
if (brp_2 >= aarch64->brp_num) {
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
return ERROR_FAIL;
}
breakpoint->set = brp_1 + 1;
- breakpoint->linked_BRP = brp_2;
- control_CTX = ((CTX_machmode & 0x7) << 20)
+ breakpoint->linked_brp = brp_2;
+ control_ctx = ((ctx_machmode & 0x7) << 20)
| (brp_2 << 16)
| (0 << 14)
- | (CTX_byte_addr_select << 5)
+ | (ctx_byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_1].used = 1;
brp_list[brp_1].value = (breakpoint->asid);
- brp_list[brp_1].control = control_CTX;
+ brp_list[brp_1].control = control_ctx;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].brpn,
brp_list[brp_1].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].brpn,
brp_list[brp_1].control);
if (retval != ERROR_OK)
return retval;
- control_IVA = ((IVA_machmode & 0x7) << 20)
+ control_iva = ((iva_machmode & 0x7) << 20)
| (brp_1 << 16)
| (1 << 13)
- | (IVA_byte_addr_select << 5)
+ | (iva_byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_2].used = 1;
brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
- brp_list[brp_2].control = control_IVA;
+ brp_list[brp_2].control = control_iva;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn,
brp_list[brp_2].value & 0xFFFFFFFF);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].BRPn,
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].brpn,
brp_list[brp_2].value >> 32);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].brpn,
brp_list[brp_2].control);
if (retval != ERROR_OK)
return retval;
if (breakpoint->type == BKPT_HARD) {
if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
int brp_i = breakpoint->set - 1;
- int brp_j = breakpoint->linked_BRP;
+ int brp_j = breakpoint->linked_brp;
if ((brp_i < 0) || (brp_i >= aarch64->brp_num)) {
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
(uint32_t)brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
(uint32_t)brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
brp_list[brp_j].value = 0;
brp_list[brp_j].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].brpn,
brp_list[brp_j].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].brpn,
(uint32_t)brp_list[brp_j].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].BRPn,
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].brpn,
(uint32_t)brp_list[brp_j].value);
if (retval != ERROR_OK)
return retval;
- breakpoint->linked_BRP = 0;
+ breakpoint->linked_brp = 0;
breakpoint->set = 0;
return ERROR_OK;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
(uint32_t)brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
wp_list[wp_i].control = control;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].BRPn,
+ + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
(uint32_t)(wp_list[wp_i].value & 0xFFFFFFFF));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].BRPn,
+ + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
(uint32_t)(wp_list[wp_i].value >> 32));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].BRPn,
+ + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
control);
if (retval != ERROR_OK)
return retval;
wp_list[wp_i].value = 0;
wp_list[wp_i].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].BRPn,
+ + CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
wp_list[wp_i].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].BRPn,
+ + CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
wp_list[wp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].BRPn,
+ + CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
(uint32_t)wp_list[wp_i].value);
if (retval != ERROR_OK)
return retval;
struct armv8_common *armv8 = target_to_armv8(target);
- uint64_t exception_address;
+ target_addr_t exception_address;
struct watchpoint *wp;
exception_address = armv8->dpm.wp_addr;
if (exception_address == 0xFFFFFFFF)
return ERROR_FAIL;
- /**********************************************************/
- /* see if a watchpoint address matches a value read from */
- /* the EDWAR register. Testing shows that on some ARM CPUs*/
- /* the EDWAR value needs to have 8 added to it so we add */
- /* that check as well not sure if that is a core bug) */
- /**********************************************************/
- for (exception_address = armv8->dpm.wp_addr; exception_address <= (armv8->dpm.wp_addr + 8);
- exception_address += 8) {
- for (wp = target->watchpoints; wp; wp = wp->next) {
- if ((exception_address >= wp->address) && (exception_address < (wp->address + wp->length))) {
- *hit_watchpoint = wp;
- if (exception_address != armv8->dpm.wp_addr)
- LOG_DEBUG("watchpoint hit required EDWAR to be increased by 8");
- return ERROR_OK;
- }
+ for (wp = target->watchpoints; wp; wp = wp->next)
+ if (exception_address >= wp->address && exception_address < (wp->address + wp->length)) {
+ *hit_watchpoint = wp;
+ return ERROR_OK;
}
- }
return ERROR_FAIL;
}
uint32_t tmp0, tmp1, tmp2, tmp3;
debug = ttypr = cpuid = 0;
- if (pc == NULL)
+ if (!pc)
return ERROR_FAIL;
if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
armv8->debug_ap->memaccess_tck = 10;
if (!target->dbgbase_set) {
- uint32_t dbgbase;
+ target_addr_t dbgbase;
/* Get ROM Table base */
uint32_t apid;
int32_t coreidx = target->coreid;
retval = dap_get_debugbase(armv8->debug_ap, &dbgbase, &apid);
if (retval != ERROR_OK)
return retval;
- /* Lookup 0x15 -- Processor DAP */
- retval = dap_lookup_cs_component(armv8->debug_ap, dbgbase, 0x15,
+ /* Lookup Processor DAP */
+ retval = dap_lookup_cs_component(armv8->debug_ap, dbgbase, ARM_CS_C9_DEVTYPE_CORE_DEBUG,
&armv8->debug_base, &coreidx);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32
+ LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT
" apid: %08" PRIx32, coreidx, armv8->debug_base, apid);
} else
armv8->debug_base = target->dbgbase;
LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
LOG_DEBUG("debug = 0x%08" PRIx64, debug);
- if (pc->cti == NULL)
+ if (!pc->cti)
return ERROR_FAIL;
armv8->cti = pc->cti;
aarch64->brp_list[i].type = BRP_CONTEXT;
aarch64->brp_list[i].value = 0;
aarch64->brp_list[i].control = 0;
- aarch64->brp_list[i].BRPn = i;
+ aarch64->brp_list[i].brpn = i;
}
/* Setup Watchpoint Register Pairs */
aarch64->wp_list[i].type = BRP_NORMAL;
aarch64->wp_list[i].value = 0;
aarch64->wp_list[i].control = 0;
- aarch64->wp_list[i].BRPn = i;
+ aarch64->wp_list[i].brpn = i;
}
LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints",
return ERROR_FAIL;
aarch64 = calloc(1, sizeof(struct aarch64_common));
- if (aarch64 == NULL) {
+ if (!aarch64) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
CFG_CTI,
};
-static const Jim_Nvp nvp_config_opts[] = {
+static const struct jim_nvp nvp_config_opts[] = {
{ .name = "-cti", .value = CFG_CTI },
{ .name = NULL, .value = -1 }
};
-static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi)
+static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
{
struct aarch64_private_config *pc;
- Jim_Nvp *n;
+ struct jim_nvp *n;
int e;
pc = (struct aarch64_private_config *)target->private_config;
- if (pc == NULL) {
+ if (!pc) {
pc = calloc(1, sizeof(struct aarch64_private_config));
pc->adiv5_config.ap_num = DP_APSEL_INVALID;
target->private_config = pc;
Jim_SetEmptyResult(goi->interp);
/* check first if topmost item is for us */
- e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
+ e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
goi->argv[0], &n);
if (e != JIM_OK)
return JIM_CONTINUE;
- e = Jim_GetOpt_Obj(goi, NULL);
+ e = jim_getopt_obj(goi, NULL);
if (e != JIM_OK)
return e;
if (goi->isconfigure) {
Jim_Obj *o_cti;
struct arm_cti *cti;
- e = Jim_GetOpt_Obj(goi, &o_cti);
+ e = jim_getopt_obj(goi, &o_cti);
if (e != JIM_OK)
return e;
cti = cti_instance_by_jim_obj(goi->interp, o_cti);
- if (cti == NULL) {
+ if (!cti) {
Jim_SetResultString(goi->interp, "CTI name invalid!", -1);
return JIM_ERR;
}
return JIM_ERR;
}
- if (pc == NULL || pc->cti == NULL) {
+ if (!pc || !pc->cti) {
Jim_SetResultString(goi->interp, "CTI not configured", -1);
return JIM_ERR;
}
{
struct target *target = get_current_target(CMD_CTX);
- if (target == NULL) {
+ if (!target) {
LOG_ERROR("No target selected");
return ERROR_FAIL;
}
struct target *target = get_current_target(CMD_CTX);
struct aarch64_common *aarch64 = target_to_aarch64(target);
- static const Jim_Nvp nvp_maskisr_modes[] = {
+ static const struct jim_nvp nvp_maskisr_modes[] = {
{ .name = "off", .value = AARCH64_ISRMASK_OFF },
{ .name = "on", .value = AARCH64_ISRMASK_ON },
{ .name = NULL, .value = -1 },
};
- const Jim_Nvp *n;
+ const struct jim_nvp *n;
if (CMD_ARGC > 0) {
- n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
- if (n->name == NULL) {
+ n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
+ if (!n->name) {
LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
aarch64->isrmasking_mode = n->value;
}
- n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode);
+ n = jim_nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode);
command_print(CMD, "aarch64 interrupt mask %s", n->name);
return ERROR_OK;
}
context = current_command_context(interp);
- assert(context != NULL);
+ assert(context);
target = get_current_target(context);
- if (target == NULL) {
+ if (!target) {
LOG_ERROR("%s: no current target", __func__);
return JIM_ERR;
}
int cpnum;
uint32_t op1;
uint32_t op2;
- uint32_t CRn;
- uint32_t CRm;
+ uint32_t crn;
+ uint32_t crm;
uint32_t value;
long l;
"CRn", (int) l);
return JIM_ERR;
}
- CRn = l;
+ crn = l;
retval = Jim_GetLong(interp, argv[4], &l);
if (retval != JIM_OK)
"CRm", (int) l);
return JIM_ERR;
}
- CRm = l;
+ crm = l;
retval = Jim_GetLong(interp, argv[5], &l);
if (retval != JIM_OK)
value = l;
/* NOTE: parameters reordered! */
- /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
- retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
+ /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
+ retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
if (retval != ERROR_OK)
return JIM_ERR;
} else {
/* NOTE: parameters reordered! */
- /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
- retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
+ /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
+ retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
if (retval != ERROR_OK)
return JIM_ERR;
projects / fw / openocd / blobdiff