armv7a: read ttbcr and ttb0/1 at every entry in debug state

[fw/openocd] / src / target / Makefile.am

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 597070c4b86b0b4e4814fea10dc2face80694a07..fcc23adbe506946a930dd8349cd72b6dba624e91 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -19,6 +19,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
        $(AVR32_SRC) \
        $(MIPS32_SRC) \
        $(NDS32_SRC) \
+       $(STM8_SRC) \
        $(INTEL_IA32_SRC) \
        %D%/avrt.c \
        %D%/dsp563xx.c \
@@ -38,6 +39,7 @@ TARGET_CORE_SRC = \
        %D%/target.c \
        %D%/target_request.c \
        %D%/testee.c \
+       %D%/semihosting_common.c \
        %D%/smp.c
 
 ARMV4_5_SRC = \
@@ -87,6 +89,7 @@ ARM_DEBUG_SRC = \
        %D%/arm_simulator.c \
        %D%/arm_semihosting.c \
        %D%/arm_adi_v5.c \
+       %D%/arm_dap.c \
        %D%/armv7a_cache.c \
        %D%/armv7a_cache_l2x.c \
        %D%/adi_v5_jtag.c \
@@ -124,6 +127,9 @@ NDS32_SRC = \
        %D%/nds32_v3m.c \
        %D%/nds32_aice.c
 
+STM8_SRC = \
+       %D%/stm8.c
+
 INTEL_IA32_SRC = \
        %D%/quark_x10xx.c \
        %D%/quark_d20xx.c \
@@ -205,6 +211,8 @@ INTEL_IA32_SRC = \
        %D%/nds32_v3.h \
        %D%/nds32_v3m.h \
        %D%/nds32_aice.h \
+       %D%/semihosting_common.h \
+       %D%/stm8.h \
        %D%/lakemont.h \
        %D%/x86_32_common.h \
        %D%/arm_cti.h