$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
+ $(ESIRISC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
%D%/armv7m_trace.c \
%D%/cortex_m.c \
%D%/armv7a.c \
+ %D%/armv7a_mmu.c \
%D%/cortex_a.c \
%D%/ls1_sap.c \
%D%/mem_ap.c
%D%/lakemont.c \
%D%/x86_32_common.c
+ESIRISC_SRC = \
+ %D%/esirisc.c \
+ %D%/esirisc_jtag.c \
+ %D%/esirisc_trace.c
+
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
%D%/arm_adi_v5.h \
%D%/armv7a_cache.h \
%D%/armv7a_cache_l2x.h \
+ %D%/armv7a_mmu.h \
%D%/arm_disassembler.h \
%D%/arm_opcodes.h \
%D%/arm_simulator.h \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
- %D%/arm_cti.h
+ %D%/arm_cti.h \
+ %D%/esirisc.h \
+ %D%/esirisc_jtag.h \
+ %D%/esirisc_regs.h \
+ %D%/esirisc_trace.h
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am