target/armv7a_cache_l2x: change prototype of arm7a_handle_l2x_cache_info_command()

[fw/openocd] / src / target / Makefile.am

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index fcc23adbe506946a930dd8349cd72b6dba624e91..afa5f49b6b91edfb105d0c52ac82698f85444140 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -4,7 +4,9 @@ else
 OOCD_TRACE_FILES =
 endif
 
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+       %D%/riscv/libriscv.la
+
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -21,6 +23,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
        $(NDS32_SRC) \
        $(STM8_SRC) \
        $(INTEL_IA32_SRC) \
+       $(ESIRISC_SRC) \
        %D%/avrt.c \
        %D%/dsp563xx.c \
        %D%/dsp563xx_once.c \
@@ -72,8 +75,10 @@ ARMV7_SRC = \
        %D%/armv7m_trace.c \
        %D%/cortex_m.c \
        %D%/armv7a.c \
+       %D%/armv7a_mmu.c \
        %D%/cortex_a.c \
-       %D%/ls1_sap.c
+       %D%/ls1_sap.c \
+       %D%/mem_ap.c
 
 ARMV8_SRC = \
        %D%/armv8_dpm.c \
@@ -136,6 +141,11 @@ INTEL_IA32_SRC = \
        %D%/lakemont.c \
        %D%/x86_32_common.c
 
+ESIRISC_SRC = \
+       %D%/esirisc.c \
+       %D%/esirisc_jtag.c \
+       %D%/esirisc_trace.c
+
 %C%_libtarget_la_SOURCES += \
        %D%/algorithm.h \
        %D%/arm.h \
@@ -144,6 +154,7 @@ INTEL_IA32_SRC = \
        %D%/arm_adi_v5.h \
        %D%/armv7a_cache.h \
        %D%/armv7a_cache_l2x.h \
+       %D%/armv7a_mmu.h \
        %D%/arm_disassembler.h \
        %D%/arm_opcodes.h \
        %D%/arm_simulator.h \
@@ -215,6 +226,11 @@ INTEL_IA32_SRC = \
        %D%/stm8.h \
        %D%/lakemont.h \
        %D%/x86_32_common.h \
-       %D%/arm_cti.h
+       %D%/arm_cti.h \
+       %D%/esirisc.h \
+       %D%/esirisc_jtag.h \
+       %D%/esirisc_regs.h \
+       %D%/esirisc_trace.h
 
 include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am