target/armv7m: rework Cortex-M register handling part 1

[fw/openocd] / src / target / Makefile.am

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 42d809d0196fcabca14bdcdf30fb655bc06fc2b5..19ba7714e1555a1320c7daad18724e74be4b4062 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -7,6 +7,7 @@ endif
 %C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
        %D%/riscv/libriscv.la
 
+%C%_libtarget_la_CPPFLAGS = $(AM_CPPFLAGS)
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -33,6 +34,11 @@ noinst_LTLIBRARIES += %D%/libtarget.la
        $(ARMV8_SRC) \
        $(MIPS64_SRC)
 
+if HAVE_CAPSTONE
+%C%_libtarget_la_CPPFLAGS += $(CAPSTONE_CFLAGS)
+%C%_libtarget_la_LIBADD += $(CAPSTONE_LIBS)
+endif
+
 TARGET_CORE_SRC = \
        %D%/algorithm.c \
        %D%/register.c \
@@ -83,6 +89,7 @@ ARMV8_SRC = \
        %D%/armv8_dpm.c \
        %D%/armv8_opcodes.c \
        %D%/aarch64.c \
+       %D%/a64_disassembler.c \
        %D%/armv8.c \
        %D%/armv8_cache.c
 
@@ -170,6 +177,7 @@ ARC_SRC = \
        %D%/armv7a_cache_l2x.h \
        %D%/armv7a_mmu.h \
        %D%/arm_disassembler.h \
+       %D%/a64_disassembler.h \
        %D%/arm_opcodes.h \
        %D%/arm_simulator.h \
        %D%/arm_semihosting.h \