target/arm_adi_v5: fix sync CSW cache on apreg write

[fw/openocd] / src / target / Makefile.am

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 4b7c8c076c15d9b83edf3384204381fc774482ca..05f174870015938ee355d0c94ccf83c1f2d20c87 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -23,6 +23,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
        $(NDS32_SRC) \
        $(STM8_SRC) \
        $(INTEL_IA32_SRC) \
+       $(ESIRISC_SRC) \
        %D%/avrt.c \
        %D%/dsp563xx.c \
        %D%/dsp563xx_once.c \
@@ -139,6 +140,10 @@ INTEL_IA32_SRC = \
        %D%/lakemont.c \
        %D%/x86_32_common.c
 
+ESIRISC_SRC = \
+       %D%/esirisc.c \
+       %D%/esirisc_jtag.c
+
 %C%_libtarget_la_SOURCES += \
        %D%/algorithm.h \
        %D%/arm.h \
@@ -218,7 +223,10 @@ INTEL_IA32_SRC = \
        %D%/stm8.h \
        %D%/lakemont.h \
        %D%/x86_32_common.h \
-       %D%/arm_cti.h
+       %D%/arm_cti.h \
+       %D%/esirisc.h \
+       %D%/esirisc_jtag.h \
+       %D%/esirisc_regs.h
 
 include %D%/openrisc/Makefile.am
 include %D%/riscv/Makefile.am