#endif
static void
-_ao_usart_rx(struct ao_stm_usart *usart, int stdin)
+_ao_usart_rx(struct ao_stm_usart *usart, int is_stdin)
{
if (usart->reg->isr & (1 << STM_USART_ISR_RXNE)) {
usart->reg->icr = (1 << STM_USART_ICR_ORECF);
if (!ao_fifo_full(usart->rx_fifo)) {
ao_fifo_insert(usart->rx_fifo, usart->reg->rdr);
ao_wakeup(&usart->rx_fifo);
- if (stdin)
+ if (is_stdin)
ao_wakeup(&ao_stdin_ready);
#if HAS_SERIAL_SW_FLOW
/* If the fifo is nearly full, turn off RTS and wait
}
#endif
} else {
- usart->reg->cr1 &= ~(1 << STM_USART_CR1_RXNEIE);
+ usart->reg->cr1 &= ~(1UL << STM_USART_CR1_RXNEIE);
}
}
}
static void
-ao_usart_isr(struct ao_stm_usart *usart, int stdin)
+ao_usart_isr(struct ao_stm_usart *usart, int is_stdin)
{
- _ao_usart_rx(usart, stdin);
+ _ao_usart_rx(usart, is_stdin);
if (!_ao_usart_tx_start(usart))
- usart->reg->cr1 &= ~(1<< STM_USART_CR1_TXEIE);
+ usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TXEIE);
if (usart->reg->isr & (1 << STM_USART_ISR_TC)) {
usart->tx_running = 0;
- usart->reg->cr1 &= ~(1 << STM_USART_CR1_TCIE);
+ usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TCIE);
if (usart->draining) {
usart->draining = 0;
ao_wakeup(&usart->tx_fifo);
}
static inline uint8_t
-_ao_usart_sleep_for(struct ao_stm_usart *usart, uint16_t timeout)
+_ao_usart_sleep_for(struct ao_stm_usart *usart, AO_TICK_TYPE timeout)
{
return ao_sleep_for(&usart->rx_fifo, timeout);
}
}
static void
-ao_usart_init(struct ao_stm_usart *usart)
+ao_usart_init(struct ao_stm_usart *usart, int hw_flow)
{
usart->reg->cr1 = ((0 << STM_USART_CR1_M1) |
(0 << STM_USART_CR1_EOBIE) |
(0 << STM_USART_CR2_LBDL) |
(0 << STM_USART_CR2_ADDM7));
- usart->reg->cr3 = ((0 << STM_USART_CR3_WUFIE) |
- (0 << STM_USART_CR3_WUS) |
- (0 << STM_USART_CR3_SCARCNT) |
- (0 << STM_USART_CR3_DEP) |
- (0 << STM_USART_CR3_DEM) |
- (0 << STM_USART_CR3_DDRE) |
- (0 << STM_USART_CR3_OVRDIS) |
- (0 << STM_USART_CR3_ONEBIT) |
- (0 << STM_USART_CR3_CTIIE) |
- (0 << STM_USART_CR3_CTSE) |
- (0 << STM_USART_CR3_RTSE) |
- (0 << STM_USART_CR3_DMAT) |
- (0 << STM_USART_CR3_DMAR) |
- (0 << STM_USART_CR3_SCEN) |
- (0 << STM_USART_CR3_NACK) |
- (0 << STM_USART_CR3_HDSEL) |
- (0 << STM_USART_CR3_IRLP) |
- (0 << STM_USART_CR3_IREN) |
- (0 << STM_USART_CR3_EIE));
-
+ uint32_t cr3 = ((0 << STM_USART_CR3_WUFIE) |
+ (0 << STM_USART_CR3_WUS) |
+ (0 << STM_USART_CR3_SCARCNT) |
+ (0 << STM_USART_CR3_DEP) |
+ (0 << STM_USART_CR3_DEM) |
+ (0 << STM_USART_CR3_DDRE) |
+ (0 << STM_USART_CR3_OVRDIS) |
+ (0 << STM_USART_CR3_ONEBIT) |
+ (0 << STM_USART_CR3_CTIIE) |
+ (0 << STM_USART_CR3_CTSE) |
+ (0 << STM_USART_CR3_RTSE) |
+ (0 << STM_USART_CR3_DMAT) |
+ (0 << STM_USART_CR3_DMAR) |
+ (0 << STM_USART_CR3_SCEN) |
+ (0 << STM_USART_CR3_NACK) |
+ (0 << STM_USART_CR3_HDSEL) |
+ (0 << STM_USART_CR3_IRLP) |
+ (0 << STM_USART_CR3_IREN) |
+ (0 << STM_USART_CR3_EIE));
+
+ if (hw_flow)
+ cr3 |= ((1 << STM_USART_CR3_CTSE) |
+ (1 << STM_USART_CR3_RTSE));
+
+ usart->reg->cr3 = cr3;
/* Pick a 9600 baud rate */
ao_usart_set_speed(usart, AO_SERIAL_SPEED_9600);
/* Enable the usart */
usart->reg->cr1 |= (1 << STM_USART_CR1_UE);
-
}
-#if HAS_SERIAL_HW_FLOW
-static void
-ao_usart_set_flow(struct ao_stm_usart *usart)
-{
- usart->reg->cr3 |= ((1 << STM_USART_CR3_CTSE) |
- (1 << STM_USART_CR3_RTSE));
-}
-#endif
-
#if HAS_SERIAL_1
struct ao_stm_usart ao_stm_usart1;
}
uint8_t
-_ao_serial1_sleep_for(uint16_t timeout)
+_ao_serial1_sleep_for(AO_TICK_TYPE timeout)
{
return _ao_usart_sleep_for(&ao_stm_usart1, timeout);
}
}
uint8_t
-_ao_serial2_sleep_for(uint16_t timeout)
+_ao_serial2_sleep_for(AO_TICK_TYPE timeout)
{
return _ao_usart_sleep_for(&ao_stm_usart2, timeout);
}
}
#endif
+void
+ao_serial_shutdown(void)
+{
+#if HAS_SERIAL_1
+ stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_USART1EN);
+#endif
+#if HAS_SERIAL_2
+ stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USART2EN);
+#endif
+}
+
void
ao_serial_init(void)
{
*/
#if SERIAL_1_PA9_PA10
- stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
+ ao_enable_port(&stm_gpioa);
stm_afr_set(&stm_gpioa, 9, STM_AFR_AF1);
stm_afr_set(&stm_gpioa, 10, STM_AFR_AF1);
#else
#if SERIAL_1_PB6_PB7
- stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
+ ao_enable_port(&stm_gpiob);
stm_afr_set(&stm_gpiob, 6, STM_AFR_AF0);
stm_afr_set(&stm_gpiob, 7, STM_AFR_AF0);
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_USART1EN);
ao_stm_usart1.reg = &stm_usart1;
- ao_usart_init(&ao_stm_usart1);
+ ao_usart_init(&ao_stm_usart1, 0);
stm_nvic_set_enable(STM_ISR_USART1_POS);
stm_nvic_set_priority(STM_ISR_USART1_POS, 4);
*/
# if SERIAL_2_PA2_PA3
- stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
-
+ ao_enable_port(&stm_gpioa);
stm_afr_set(&stm_gpioa, 2, STM_AFR_AF1);
stm_afr_set(&stm_gpioa, 3, STM_AFR_AF1);
# if USE_SERIAL_2_FLOW
# endif
# else
# if SERIAL_2_PA14_PA15
- stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
-
+ ao_enable_port(&stm_gpioa);
stm_afr_set(&stm_gpioa, 14, STM_AFR_AF1);
stm_afr_set(&stm_gpioa, 15, STM_AFR_AF1);
# if USE_SERIAL_2_FLOW
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USART2EN);
ao_stm_usart2.reg = &stm_usart2;
- ao_usart_init(&ao_stm_usart2);
-# if USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW
- ao_usart_set_flow(&ao_stm_usart2);
-# endif
+ ao_usart_init(&ao_stm_usart2, USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW);
stm_nvic_set_enable(STM_ISR_USART2_POS);
stm_nvic_set_priority(STM_ISR_USART2_POS, 4);