AO_DATA_PRESENT(AO_DATA_ADC);
ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
- if (ao_data_present == AO_DATA_ALL) {
-#if HAS_MS5607
- ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
-#endif
-#if HAS_MMA655X
- ao_data_ring[ao_data_head].mma655x = ao_mma655x_current;
-#endif
-#if HAS_HMC5883
- ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
-#endif
-#if HAS_MPU6000
- ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
-#endif
- ao_data_ring[ao_data_head].tick = ao_tick_count;
- ao_data_head = ao_data_ring_next(ao_data_head);
- ao_wakeup((void *) &ao_data_head);
- }
+ ao_data_fill(ao_data_head);
ao_adc_ready = 1;
}
int ch;
uint16_t value;
- ao_cmd_decimal();
+ ch = ao_cmd_decimal();
if (ao_cmd_status != ao_cmd_success)
return;
- ch = ao_cmd_lex_i;
if (ch < 0 || AO_NUM_ADC <= ch) {
ao_cmd_status = ao_cmd_syntax_error;
return;
}
#endif
-__code struct ao_cmds ao_adc_cmds[] = {
+const struct ao_cmds ao_adc_cmds[] = {
{ ao_adc_dump, "a\0Display current ADC values" },
#if AO_ADC_DEBUG
{ ao_adc_one, "A ch\0Display one ADC channel" },
/* Reset ADC */
stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
- stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
+ stm_rcc.apb2rstr &= ~(1UL << STM_RCC_APB2RSTR_ADCRST);
/* Turn on ADC pins */
stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
#endif
/* Wait for ADC to be idle */
- while (stm_adc.cr & ((1 << STM_ADC_CR_ADCAL) |
- (1 << STM_ADC_CR_ADDIS)))
+ while (stm_adc.cr & ((1UL << STM_ADC_CR_ADCAL) |
+ (1UL << STM_ADC_CR_ADDIS)))
;
/* Disable */
}
/* Turn off everything */
- stm_adc.cr &= ~((1 << STM_ADC_CR_ADCAL) |
- (1 << STM_ADC_CR_ADSTP) |
- (1 << STM_ADC_CR_ADSTART) |
- (1 << STM_ADC_CR_ADEN));
+ stm_adc.cr &= ~((1UL << STM_ADC_CR_ADCAL) |
+ (1UL << STM_ADC_CR_ADSTP) |
+ (1UL << STM_ADC_CR_ADSTART) |
+ (1UL << STM_ADC_CR_ADEN));
/* Configure */
stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) | /* analog watchdog channel 0 */
(0 << STM_ADC_CCR_VREFEN));
/* Calibrate */
- stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
- while ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) != 0)
+ stm_adc.cr |= (1UL << STM_ADC_CR_ADCAL);
+ while ((stm_adc.cr & (1UL << STM_ADC_CR_ADCAL)) != 0)
;
/* Enable */
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
/* Set ADC to use DMA channel 1 (option 1) */
- stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
+ stm_syscfg.cfgr1 &= ~(1UL << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));